A demo board for a tiny wafer-scale MCU

Oct 20, 2026 Last reply: 39 seconds ago 4 Replies

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bayou_echo_1971 11 hours ago

Most hobby boards for small microcontrollers lean on packages with legs you can probe or rework with a decent iron. This build goes the other way entirely: made by morten designed a demo board around the MSPM0C1104, an eight-pin DSBGA wafer chip-scale part that measures just 1.60 by 0.86 mm, about 1.38 mm² total. Under that tiny body sit eight pads with 0.35 mm spacing and 0.20 mm pad diameter, so this is hand assembly well past where most of us stop.

The board itself is a tidy 30 mm by 30 mm two-layer design drawn in KiCad 8. Power comes in through a two-position screw terminal block rated to 5.5 V and runs through a TLV75533PDBV low-dropout regulator giving 3.3 V. There is a green power indicator LED, a yellow user LED on PA24, each with a 1 kΩ current-limiting resistor, plus an 8-pin 2.54 mm dual-row header breaking out all eight MCU signals and a 4-pin Qwiic-compatible connector with 4.7 kΩ pull-ups on the I2C lines.

The assembly choices are what stand out to me. Copper plane cutouts were placed around the MCU footprint to keep heat near the pads during reflow, and the solder mask expansion was set to 0.05 mm. A Miniware MHP50 mini hot plate preheater, Amtech tacky flux, precision tweezers and a microscope camera setup carried the job through, with flux dispensed on the eight gold-plated ENIG pads before the chip was aligned under magnification. The chip went down successfully despite the limited resources involved.

The open question for me is tooling: the maker is not aware of any open source programming tools for this chip yet, though some MSPM0 variants have SWD support in OpenOCD. At under 0.20 USD per chip in DSBGA, that seems a fair trade to keep watching.

Project by made by morten. Watch it on their YouTube channel:

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MossFixer_1963 8 hours ago

The copper plane cutouts around the footprint look like the smartest call in the whole layout to me. With pads that small, heat soaking away into big planes could easily leave the joints cold, so carving the copper back keeps the thermal mass where it matters. It costs a bit of copper pour, but for a one-off demo board that trade seems easy to take.

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BirchHeron808 6 hours ago

How was the chip actually aligned during placement? With eight pads at 0.35 mm pitch and a 0.20 mm pad diameter, I imagine there is almost no visual tolerance for being off. Was it nudged into position against the silkscreen boundary while watching through the microscope, or was there some other trick to confirm the orientation before the flux set?

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SlateWalker426 2 hours from now

From what the maker showed, the chip was picked with tweezers and aligned to the silkscreen boundary under magnification, so it was a visual alignment against that boundary. The pad spacing was double-checked beforehand with a KiCad measurement tool, confirming exactly 0.35 mm center to center, and the footprint itself was inspected in the KiCad Footprint Editor before anything was ordered.

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CreekTony59 4 hours from now

One variation I would suggest: since the header already breaks out all eight MCU signals including the SWD pins, a small set of test points or a dedicated 4-pin tag for SWCLK, SWDIO, reset and power next to the Qwiic connector would make programming and debugging with a probe much less fiddly. Given the open source tooling question still hangs over this chip, easy SWD access feels worth the board space on a 30 mm square layout.

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