15 discussions on ElectronDepot about the Xilinx XC3000: what owners asked, what went wrong, and what fixed it.
I am looking at a design that was done several years back which usesseveral XC3000 devices. All devices are programmed with the same corefrom a computer on power up. What I am seeing is that once or twice ayear, one of the devices will...
This is likely not a big deal to most, but it hurts me a lot. I have one product in production and it uses an XP device. They are only giving until November to get your last time buy orders in. I think Lattice is doing a disservice to...
We use in a laboratory course still XILINX XC3000 FPGAs withViewlogic's Workview design entry (DOS version) and XILINXXACT (also DOS). The problem is that we have to replace the old PC's and that Viewlogic only supports a few graphics modes...
Witam!zastanawiam sie jak zrobic w VHDL 8-bitowy rejestr, ktory mozna podlaczyc do wspolnej trojstanowej szyny IO (szyna wewnetrzna w scalaku) ze strobem zapisu i odczytu?Chodzi o to, zeby przy wr=0 rejest zapamietywal to co jest na szynie,...
HiI know many wise men has said NO NO, but1)Lattice engineer suggest that it works (assumable reliable) on machXOthe IO technology between machXO and Xilinx FPGAs isnt so big so Iwonder why cant it be done with Xilinx ?for what I see is...
Hello,Don't know if this is the right place to report this, but...While reading some xilinx docs I came across the following typos:* ug071 v1.4, table 7-5 page 91, the column address spans bits 13:6* ug191 v1.2, table 6-7 page 103, the...