The MPF102 is really too wimpy for this circuit, an MPF112/HEP801 with the appropriate bias changes would work MUCH better
That would work fine.... no emitter follower necessary.
If you can see *any* distortion using an oscilloscope, your oscillator is not running as a phase-shift oscillator. The one I breadboarded gives a perfect looking sinewave. I would bet that if I hooked it up to my distortion analyzer it would be well under 1%
See John Jardine's note about my original circuit. When I breadboarded it with the 100uf source cap, and the 22K drain it was oscillating in a wierd way. Changing the drain resistor to 47K, and upping the cap stopped that and it started to behave as a real phase-shift oscillator should... Clean and high amplitude. It also runs from 7v to 15v with no problems.
He says "Since a rigorous solution is messy to calculate, we estimate." In another posting I gave the exact value of 18.3878.
On this same web site an expression is given for the frequency of oscillation as "f = 1 / (2 * pi * SQRT(6) * R * C). This looks like the expression for a 3 section phase shift network, not a 4 section network. And the expression is wrong anyway if it is for a 3 section network. The correct expression is SQRT(6)/(2 * Pi * R * C).
For a 4 section network with all the same Rs and Cs, the expression for the frequency of oscillation is SQRT(10/7)/(2 * Pi * R * C).
There is a complete solution for the 3 section equal valued network at:
formatting link
Could you measure the Idss of your MPF102? Short the gate and source together, apply
15 volts to the drain and measure the current. Should be a min of 2 mA and a max of 20 mA. Measure quickly before it heats up. If you only apply 9 volts, Idss will be a little smaller, but that value will still give us some information about your particular FET.
Well, I've simulared your simulation with the Real Thing, which has four sections. It does oscillate. Maybe my mistake is to use such a large (3200uF) source bypass cap. I've got a 33k drain resistor, with less than 6.6V (which is 200 uA) across it.
I think that the series combination of the 33k drain resistor, the four
220k resistors, and the 4.3M gate resistor, and the 10 uF cap, takes several minutes to charge the cap. One time constant is about 56.5 seconds, or over 1 minute. This and the source byp cap are causing the osc's to damp out after several minutes. I'm going to have to reduce them and see if it helps.
My Moto manual is too old to have the MPF112 but I have the HEP catalog with the HEP 801 in it, and I posted the other followup with a comparison of the three JFETs. Refer to it. The noticeable diff is the
801 has a min Gm of 3000 but not much diff otherwise.
on
on
change
to
gives
Well, right now I can't get it to keep oscillating, as the caps charge it goes past the optimum bias point and then when it finally stabilizes after several more minutes, it damps out. So it's hard to tell where it's at 'cause it keeps changing. I'll have to fiddle some more with the source resistor and diodes to get it to stabilize.
breadboarded
I haven't tried more than three JFETs in the circuit, but I have a bagful that I can swap if I put a socket in the stripboard. Have you tried more than one JFET to see if it makes a diff? I think that with such a wide a tolerance in specs, the MPF102 would make a really poor choice for a production run, because every unit would have to be adjusted to get it to be working optimum.
Right now, I'm just trying to get it to be stable and keep oscillating. It's trying its best to misbehave.
Since you are getting oscillations at such a low frequency, you can just put a 10 meg resistor in series with the probe tip and measure the ac voltage at gate and drain and take the ratio. The probe need not be compensated for this measurement.
I still have a couple problems. I've been watching (Well TV too) this thing, and after 40 minutes it's damped out again. I changed the bias resistor, and it takes maybe ten minutes to ramp up, then it osillates for another 10 or 20 min, then it takes another ten mins to die out. So even if I take a measurement, it isn't stable enough to be certain the reading is right. I'm still working on getting the bias right.
But if I put a 10M res in series with the probe, I still have a problem. The gate resistor is 4.3M, so I've effectively got a parallel combination that's about 3.1M and as it's barely oscillating w/o the probe, I would guess it won't osc at all with it. Not to mention it's still loading down the gate.
I'm thinking it might be better to put a .8M in series with the gate res to make a 10:1 divider and take the measurement across that res.
Put a *non-electrolytic* capacitor of a few tenths of a microfarad in series with the
10 Meg resistor as well, and then the DC bias won't be upset. And you could use
*several*
10 Meg resistors. As long as your scope has enough gain so you can get a useable indication you should be able to make the measurement.
I don't think you understand what's happening. The JFET's gate has zero volts bias across the gate resistor, because it's, well, a FET, not a BJT. And at the freq we're dealing with here, the few tenths of a uF will be essentially an open.
What I'm suggesting is a way to measure the gain of your FET when the circuit is oscillating. The probe with a 10 meg resistor in series with the probe tip would give about 11 megs DC resistance which would upset your bias when connected to the gate. So if you put a 1 uF capacitor in series with the 10 megs and the combination in series with the probe tip, you will not be upsetting the bias, since there won't be a DC path through the combination (neglecting the leakage of the cap, which if it is a film cap, will be very low). I believe your frequency of oscillation is *about* 1 Hz. The impedance of a 1 uF capacitor at 1 Hz is 159K ohms which is negligible compared to the 10 meg resistor, so you should be able to get a usable signal to the scope. The change in calibration factor of the scope won't matter, since you will measure the amplitude of the approximately 1 Hz sine wave at the gate and at the drain with the same probe plus 10 meg (or more) and 1 uF in series with the probe tip. Just take the ratio of the amplitude at the drain to that at the gate and that's your amplifier gain under actual operating conditions.
No. There is _no_ voltage drop across the gate resistor because the gate is essentially an open, the leakage current is literally picoamps. The cap will not help and is not needed.
combination in series with the
DC path through the
cap, will be very
impedance of a 1 uF
meg resistor, so you
Again, the capacitor is of no help. The problem is that the impedance at the gate is 4.3M, which is so high that if you put a 11M probe on it, the added attenuation will cause the FET to stop oscillating.
I'm still having problems with maintaining oscillation. But every change I make takes the better part of an hour to find out. :-(
I suggested using a cap because I think you do in fact have some DC bias at the gate. It is possible that you are getting some slight rectification of the AC on the gate (since it's a junction FET), and the 10 uF capacitor looks to be an electrolytic (I infer this from the
sign on the left plate), and probably has enough leakage to give some gate bias. I wanted you to measure the gain in the circuit as it is. I suspect leakage from this electrolytic may be causing some of your instability problems.
(I just grabbed several 10 uF electrolytic caps, with voltage ratings from 15 to 63 volts. With 5 volts applied I get around 1 uA of leakage current. You have a DC path to the 10 uF cap through your
330K resistors, and 1 uA of leakage could raise the voltage across the
4.3 Meg resistor to several volts if it weren't for its tendency to forward bias the gate of the (junction) FET. And, of course, the leakage changes slowly with time as you apply voltage to the 10 uF cap. Then, when the circuit is powered down, the capacitor de-forms, as it were, and the leakage starts out higher and then decreases again the next time you power it up.)
This is another disadvantage of the lead form of the phase shift network that hadn't occurred to me until now. With the lag form, you would have several smaller caps in series from the drain, with a resistor at each stage to bleed off the leakage.
If you have a 10 uF film cap handy, you might try putting that in place of the electrolytic you have there now (I'm assuming it is an electrolytic now).
The AC impedance at the gate is essentially equal to the impedance of the phase shifting network looking back toward the drain. At the expected frequency of oscillation, .576 Hz, I calculate it to be
223192 ohms. This AC impedance should not be loaded very much by an
11 meg probe. On the other hand, without the 1 uF non-electrolytic capacitor in series with the probe, I would expect the 11 megs to change the DC bias which I am sure you have at the gate.
Come on Watson, there has to be a signal on the gate. A PSO is an inverting amplifier with a 180 degree lead/lag network feeding back output signal to the input.
If you truly have no signal, you have no oscillation.
There are two modes of operation going on in this oscillator: The DC biasing with its feedback stabilization, and the AC signal, with its feedback network.
The DC biasing is caused by the voltage drop in the source resistor. As the FET tries to draw too much iGD, the voltage drop on Rs increases, putting the gate more into the cutoff, or OFF, region, which reduces the voltage drop on Rs, which puts the gate less into the cutoff region, ... Because your source capacitor is huge, this will be a measurable effect all by itself, albeit a very damped one, as the bias circuit is a source follower and has a DC gain that is *always* less than one (so it is always stable).
The AC signal path is the one that has fairly high gain. It must have a gain of at least 29x for my circuit to work. This is easily measurable, remove your phase shift network, and stick a capacitor coupled, 100 millivolt signal (any audio frequency will do) into the gate, and measure the signal on the drain.
For your circuit to operate, you had better see a couple of volts on your drain!
(Conversely, if your oscillator is working, it must have about 100 mv on your gate.)
Your gain is: Av = -Vo/Vi, we are only interested in AC voltages!
The circuit is essentially the same, except that I've changed the source bias to three Si diodes in series, and a 1k resistor. I think I'll lower the 1k even lower, to get the bias point to where the sine wave swings are more symmetrical.
With the attenuation of the RC netwrok being 18, I don't see how the signal swing could be more than 9V / 18 or 1/2V peak-to-peak.
I used a larger cap before, and it was leaky, which upset the bias. I changed it to 10uF, and the leakage problem went away. I'm not saying that the 10 uF has none, just that it seems that it's much, much less than the larger cap. As a precaution, I could change it to a different cap. However I don't have a 10 uF in a non-'lytic that's anything reasonable in size. I can parallel a few 1 uFs instead. The reactance of the 10 uF is about 24k at .67Hz. If I go to a 1 uF the reactance will be 240k, which is more than 5 percent of the 4.3M gate resistor, and adds appreciably to the attenuation. In this circuit, with its damped osc problem, that can make the difference between sustained oscillation and damped.
Instability? Inability - to sustain oscillations. Before with the larger leaky cap, I couldn't get the drain more than a half volt above the source, the leakage was causing the gate to be too 'open' and let too much current thru the FET. Now, after a half hour, the oscs damp out and the drain voltage is in the 6 or 7V area, which means that the FET's gate is doing a good job of 'closing', IOW the neg voltage (measured between source and gate) is sufficient. This leads me to conclude that there isn't appreciable leakage into the gate.
I put the DMM on .2VDC range across one of the 330k resistors. It measured under 100mV when I powered on, and after maybe 4 or 5 minutes it measured under 30mV, when the readings started to fluctuate as it began oscillating. So choosing the 33mV point, .033V / 330,000 gives
1/10 uA, which when multiplied by 4.3Megs gives .43V, which isn't enough to upset the bias and is more than the actual value, when the 10uF finally gets charged up.
I think you got those reversed, above. Lead is CR, lag is RC as in the schematic above.
For the schematic above, it's a disadvantage because the JFET requires negative bias, hence DC isolation from the lag network. If it were a MOPSFET, the above schematic could be an advantage because it would be self biasing, and the four 330k resistors would be part of the bias network. IOW it would be simpler than the lead network, requiring less resistors. But yeah, the lead network would be simpler in this case with the JFET, and less prone to leakage. I started out with the CR lead network, but didn't have success maintaining oiscillations. So I switched, probably on recommendation of others here.
The one thing I like about the CR lead netork as far as BJTs go is that the waveform is less distorted because it's a low pass filter. Higher harmonics at the collector get fed back to the base where they are cancelled.
I think it's been on long enough to stabilize and the oscs are damped out. BRB. Well, the oscs are almost damped out, and I measure across one of the 330ks about 1 to 2 mV, which is about .005 uA leakage. That's less than .02V across the 4.3M bias resistor. But now that it's damped out and stable, I'll measure the DCV across the 4.3M. BRB. Well, the meter is still jumping around zero, but as best as I can tell it's swinging from neg 10mV to pos 11 or 12mV, which seems to agree somewhat with the leakage estimate. Of course I didn't include the DMM's resistance, but I think it's 100M on the 200mV range.
I'm convinced that the leakage isn't a prob, and changing the cap isn't gonna help. What do you say?? Maybe I should try a 10uF tantalum, but is that gonna be a help?
I would have to use a handful of 1 uFs, but I think I will have a huge problem with picking up a lot of extraneous noise and hum, since this huge glob of caps will all be at very high impedance and acting like a large antenna. :-(
I read in alt.binaries.schematics.electronic that Watson A.Name - "Watt Sun, the Dark Remover" wrote (in ) about 'Why Can't I get This FET To Oscillate', on Fri, 7 Jan 2005:
I don't think so. 240 kohms in quadrature with 4.3 Mohm is 4.3066.. Mohms. The attenuation is quite negligible.
--
Regards, John Woodgate, OOO - Own Opinions Only.
The good news is that nothing is compulsory.
The bad news is that everything is prohibited.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk
In another posting John pointed out that the reactive and resistive components combine in quadrature, so that the ratio of 240K to 4.3 Meg doesn't by itself indicate what the change in gain requirement will be for a change to 1 uF. As you pointed out to him in response, there is the changed phase shift to consider. One really has to analyze the full phase shift network. The 10 uF and 4.3 Meg you have there now changes the required gain also, and I thought I would calculate the numbers for the cases we're talking about.
For a network of 4 equal 330K/1uF sections, the theoritical required gain is
-18.3878
For the four sections plus the 10uF/4.3Meg the required gain is -20.0796
For the four sections plus the 10uF/4.3Meg and with 11 Megs additional to ground at the gate, the required gain is -20.7562
For the four sections plus 1uF/4.3Meg the required gain is -21.7218, so changing the 10 uF to 1 uF raises the required gain by 21.7218/20.0796, or 8.2%.
And, of course, the frequency of oscillation changes, about +7.7% from the first to last case described above.
You've really piqued my interest now. I can't imagine what would aspect of this circuit would have a time constant on the order of 1/2 hour!
Well, I guess that eliminates that issue. My capacitors came out of the parts drawers and hadn't been used for years, if ever. Yours has been getting plenty of power-up use, and the leakage has gotten comfortably low. Darn.
Yes. That's what comes of writing this at 3:00 AM.
But as I pointed out in another post, this also means that you have lots of feedback at high frequencies. The MPF102 is specified as a VHF amplifier. You could more easily have parasitic oscillations at some high radio frequency that would upset the operation of the circuit with the lead topology.
Here's a suggestion. Get rid of the components you have in the source lead now. Make a small stiff, adjustable bias supply by connecting 3 penlight alkaline cell in series. Put a 100 ohm (or thereabouts) trimpot across the 4.5 volt battery. Connect the most negative terminal of the battery to ground, and connect the source of the FET to the wiper of the trimpot. You will have gotten rid of a big capacitor and possible source of long time constant behavior, and have an easily adjustable, low impedance bias supply.
I read in alt.binaries.schematics.electronic that Watson A.Name - "Watt Sun, the Dark Remover" wrote (in ) about 'Why Can't I get This FET To Oscillate', on Fri, 7 Jan 2005:
3.2 degrees.
--
Regards, John Woodgate, OOO - Own Opinions Only.
The good news is that nothing is compulsory.
The bad news is that everything is prohibited.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk
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