Why Can't I get This FET To Oscillate

Ask Gregg t3h g33k. ;)

Tim

-- "I've got more trophies than Wayne Gretsky and the Pope combined!" - Homer Simpson Website @

OOPS! Change that 3.3uf to 100uf.

-Chuck Harris

On Mon, 03 Jan 2005 00:06:57 -0800, Watson A.Name - "Watt Sun, the Dark Remover" wrote: ...

Oy vey! Design by committee!

I rather like Chuck Harris's design, because it ups the impedance of the whole thing - he even goes all the way up to 100 uF for the source cap, ;-) but you have enough uFs there to bypass Niagara Falls, so I wouldn't worry about that! ;-)

And if I had this puppy on my breadboard, another thing I'd have tried if I'd been at the same point yesterday would be the stepped impedances in the network that John Popelish was kind enough to offer.

Good Luck! Rich

out

1.2V 3 is

V out

resistor

Well, that was what I mentioned in another followup. According to the specs, the MPF102 can have a Vgs of anywhere from .5V to 7.5V; that's a ratio of fifteen to one. In the case of the FET I chose, it seems to be working pretty good at about 1.5 V. But I'll vary it to see what effect it has.

The 330k and 1uF sections of my schem, and the 1M and .33uF sections of your schem have the same net effect because they are both loaded by the gate, which is nearly infinite impedance, so the gate is negligible. And since in both cases the impedance of the RC net is more than ten times the drain load resistor, the RC net has negligible loading effect in the drain resistor. Do you agree with this? If so, then it seems that there should be no need to change from 330k and 1 uF to 1M and .33 uF RC sections.

So after all this, it comes down to the number of sections, mine with four, and yours with three. I tried the three sections, and I could barely tell that there was some overshoot on the output waveform, it was _very_ damped. So there was a serious need for more gain or less attenuation. So I went with four sections to get less attenuation.

And I tried the 22k drain load resistor, but it was still too low. Finally when I got up into the high 20s I started to see some life in the damped oscillation. At 33k it finally was able to sustain oscillations. What I need to do now is fiddle with the source bias resistor to get the waveform to clip symmetrically. So your suggestion of changing the Vgs looks like it'll be one key to get the waveform looking reasonable.

Thanks.

wrote

L33tspeak not used here! Electronicspeak used!

Or alternately, Mathspeak. ;-)

Dark

oscillate.

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It's taking 16 seconds to do ten cycles, so the thing is oscillating at about .62 Hz. I want the byp cap Z to be at least 10 times less than the drain resistor, so 330 ohms seems okay. Using the standard formula

F = 1/(2*Pi*R*C) ---> C = 1/(2*Pi*R*F)

I get 720 uF, and started with 1000 uF. But I still measured some Ac voltage across the cap, so I decided to increase it a bit to minimize any degeneration it might cause. So upping it to four times that much didn't seem unreasonable. I can still measure a few mV change across it as it oscillates. Looks like your 100 uF is way too low.

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in

Almost every PSO I've seen uses equal values. Nothing wrong with the stepped values, tho. Except I would have had to change them. Am I lazy? I guess so. :o)

I get the following numbers:

For N sections of the lag type where each section *doesn't* load the previous section and N=3,4,5,6,7,10,100 the required amplifier gain is -G= 8, 4, 2.885, 2.37,

2.075, 1.65, 1.05

Obviously, the limiting case is where the phase shift network is replaced by a lossless delay line and the required amplifier gain is -1 (just an inverting buffer).

For 3 sections where each identical section loads the previous one, the required gain is G = -29 (the classic case)

For 4 sections where each identical section loads the previous one, the required gain is G = -18.3878

For 3 sections where each section loads the previous one and the value of R in subsequent sections is 10 times what it was in the previous section, and C is 10 times smaller, the required gain is G = -9.272. If the impedance levels increase by a factor of

100 in subsequent sections (instead of just 10), the required gain is G =

-8.1207. We are approaching the gain of exactly 8 needed for the non-loading case.

The problem is the actual gain of the stage is: Av = -RL/gm, where RL is the total load, and as such is the parallel combination of the drain resistor, and the resistance of the FET, rs. In the linear region, rs changes depending on where you bias the FET. rs is low when Vgs is near zero, and high when Vgs is very negative. To get maximal gain, you want rs to be high. Like all things, you have to reach a compromise.

I arranged the phase circuit the way I did to eliminate the need for the extra isolation capacitor, and gate resistor. The values you used are fine. I prefer high impedance because it makes for a smaller network.

Well, if you are really concerned about attenuation, you can use the classic technique of making each section of the network 10x the impedance of the last. eg:

-----0.0033---o---0.033---o---0.33---o---gate | | | 10K 100K 1M | | | G G G

Then you will only need a gain of 9 or 10 to overcome the loss of the phase shift network. (This technique works because it reduces the loading on the previous stage, and gets you closer to the theoretical stage where there is no loading on the output of any stage.)

Getting the gate biased into the correct region that gives a high value of rs is everything! If I wanted to operate with a higher voltage supply, I would then reduce Rs from 22K to 12K. That would give me clean operation at 15V, but sacrifice operation at 9V.

-Chuck Harris

and

previous section

2.37, 2.075, 1.65,

replaced by a lossless

buffer).

the required gain is

the required gain is

value of R in

and C is 10 times

increase by a factor of

G = -8.1207. We are

I don't think a ratio of ten is realistic, and 100 is out of the quwstion. The ratio of two or three seems to be what others have suggested and more realistic.

The one I'm using, with four equal sections seems to be about the only 'non-classic' version that has been in literature. I can't remember ever seeing a 'non-classic' version of a PSO that used unequal sections. Not to say that it can't be done, tho. But I'd prefer to experiment with something on which an analysis has been done.

Mine is blinking away merrily. I put an EF on it and a blue LED, so I can watch it doing its thing. On another BJT one I made, I put an amp on one of the other phases, so I get this 'one-two..' flip-flop type of flashing from the LEDs.

The main reason equal capacitors are used is to allow the frequency to be controlled by a ganged multi section variable capacitor. If fixed frequency operation is all you are trying to achieve, the stepped impedances can give you a lot more effective loop gain to support the oscillation. The two to one steps I mentioned give you almost twice the loop gain (the transistor has to provide only half the voltage gain to make the thing oscillate).

--
John Popelish

...snip

Just for grins, why don't you measure the amplitude on the gate (with at least a

10-to-1 probe, and on the drain and tell us what the actual stage gain is?

[snip]

Sheeeesh! Was all this posting about phase-shift oscillators just to accomplish a blinking LED?

A phase-shift oscillator is normally built to create SINE waves... certainly NOT the most efficient way to blink LEDs at a slow rate.

Sheeeesh!

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
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I love to cook with wine.      Sometimes I even put it in the food.

Confirming what John Popelish says, my calculations indicate a required amplifier gain of -16 for the 1:2:4 impedance taper, and a required gain of -12.8519 for the

1:3:9 taper.

For the 4 section version with a 1:2:4:8 taper, the required gain is -8.6178 and for the version with a 1:3:9:27 taper, the required gain is -6.659.

previous section

2.37, 2.075, 1.65,

replaced by a lossless

buffer).

required gain is

required gain is

of R in

is 10 times

increase by a factor of

= -8.1207. We are

Reading the previous posts it seems no one has pointed out that the circuits are not working in the way a visual inspection would suggest. The clear case in point is the neat circuit from Chuck H. He's using 3 classical HP sections and (as mentioned above) these should need a loop gain of 29 times before oscillation can even think of starting. There's no way that the MPF102 with its crap Gm, 9V supply and 22k load resistor can give anywhere near this kind of gain, yet Chuck's circuit works. Something extra is happening. The 'extra' is the 100uF "decoupling" capacitor. It's not decoupling, it's actually forming part of the phase shifting network. Essentially it's specifically "tuned" to add a fortuitous phase lag. The complicated bit is that this lag is offsetting some of the phase lead coming from the 3XRC network *while at the same time* lifting the network output voltage to a higher level. This offseting only works within a narrow range of frequencies and its effect is to give a loop phase shift of 0 degrees at a point where the output voltage of the 3XRC network is much higher than its nominal 1/29th

0deg shift would normally suggest. Hence in Chuck's case the 0 degree loop shift happens when the network has an attenuation of about 1/5th. The MPF102 can therefore easily give the X5 loop gain needed for oscillation. Problem is that the peak, source phaselag, the network voltage response shape and the network phase shift shape must all be track together or the effect fails and much more gain is needed from the FET. Change the 100uF source cap value in either direction and this "tuning" fails and oscillation ceases. The additional-lag idea though, is sufficiently robust to allow tuning of the same PSO using just 2 of it's RC sections. The clever bit is figuring a peak point for the optimum summed phase response shape wrt the network voltage response shape, given a fixed FET gain.

-----------------------

Asides ... Whilst having fun on the spice I turned up this PSO circuit. Here the MPF102 only needs a gain of .95 for clean oscillation. The 'novelty' is that the CR bandpass filter has a clean phase response and voltage gain of

1.07!. (bit of a waste for flashing a LED :-) regards john

.--------------------------. .------------------------. | Q=.25 | | | | o-------o----|-+ | | | 100k| | 0.1u| | | | | G |S | | | | | --- | | | z | | | | | 0.1u| --- | | | 2V2 A o->-' | | | --- | | | | | | | | | --- o->|--|-' V .-. | | | | | | | 2V2 z | | | | o-------o | | | | | |47k | | | | .-. | | | '-' | | | --- | | | | | | | | | --- | | | | GND GND | | | 0.1u| '-' | | | | | | 10M| | '--------------X1 Buffer-' | | o---------- | | 1u | | | | --- | | | --- .-. | | | | | | | | | |10M | | | '-' | | | | | | GND GND | | | '-----------------Bandpass-'

(created by AACircuit v1.28 beta 10/06/04

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Umm, don't you mean:

-----33u---o---3.3u----o---0.33u---o---gate | | | 10K 100K 1M | | | G G G

In which case it looks like the network will be a substantial load on the drain. So it would then be necessary to put an emitter follower on the drain just to drive the network. Maybe it would be better to change it to: (Or even higher)

----3.3u---o---.33u----o---.033u---o---gate | | | 100K 1M 10M | | | G G G

Seems that the nice thing about using a four section network is that each section does 45 degrees. That would make the reactance equal to the resistance. And this simplifies things a bit.

But others seem to favor the lag network over the lead network. For BJTs I've found that the lead network seems to have less waveform distortion than the lag.

theoretical

in

suggestion

give

Looking up the MPF102 specs, I see a minimum Gm of 2000 umhos with Vgs of zero and about 10 umhos output conductance. With a 22k drain resistor and no source resistance, this would give a gain of .002/(1/22000+1/100000) = 36. This would be with a drain current equal to Idss, but with 22k in the drain we need a drain current of less than 1mA. Otherwise we would have to put an active current source in the drain to get such a high incremental resistance without reducing Vds to nearly zero. The spec sheet curves indicate that for a drain current of .2mA, the Gm is about 1000 umhos, so we would have a gain of only 18. At any rate, the source resistor bypassing would have to be a lot better than 100 uF provides to get the amplifier phase shift to be negligible. My MicroCap simulation verifies your result, but I think a typical MPF102 should be able to provide enough gain even with a properly bypassed source resistor to oscillate with a 4 section tapered phase shift network.

G

One disadvantage of the lead network is that the transmission through the network is not rolled off at high frequencies, increasing the possibility of parasitic VHF oscillations.

Would you measure the gain from the gate to drain while it's oscillating so we can see what kind of performance might be possible with this particular FET? Be sure to use a high impedance probe on the gate.

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Why don't you just mind your own OT political discussion business.

If you don't behave, we'll send more rainstorms over you. Heh.

Dark Remover\""

required amplifier gain

for the 1:3:9 taper.

is -8.6178 and for

According to

the gain needed for four equal sections is 16. But that includes stage loading. Something said there about it would be 4 if loading is neglected.

Last night, I put an additonal diode (3 total) in series with the drain resistor, which I reduced to 1.5k. This gives a drop of 1.77V. As power is applied and the capacitors charge up, which takes several minutes, it starts oscillating. But the caps continue to charge, and after several more minutes, the oscillations damp out. The drain voltage rises to over 7V, too high. I think I've gone past the optimum point, I'll have to pot a pot in there and adjust to see where it'll keep oscillating.

So far, this is what I've got.

+9V | .-. | | 33k| | '-' | .----------------------------------------------o----o Vout | | | o-------o | .-. | | | | | | 4.3M .-. | | | 330k === | | +------o V out '-' GND | | | | '-' | | +|| | |- o---/\/\---o---/\/\--o--/\/\----o---||--o--->| JFET MPF102 | | | | || |- | 330k | 330k | 330k | 10u | | | | | o----. | | | | | | | | | | .-. | --- 1.0u --- 1.0u --- 1.0u --- 1.0u | | | + --- --- --- --- 1.5k | | --- 2 caps | | | | See '-' --- 3200uF | | | | note | | total === === === === below === === GND GND GND GNF GND GND

Note: 3 BAV21 diodes are in series with the 1.5k to give another 1.6V drop, to put more negative bias on the gate. Total drop across all is about

1.77V.

As of late Sun nite, with the above values, I got it to oscillate. Finally.

But as of Tuesday Eve, Dec 4, 05, the caps keep charging up, and the oscs die out. I think I've gone past the optimum bias point.

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