Why Can't I get This FET To Oscillate

Or use a proper oscillator ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

Of course, the ultimate is to put a follower between each stage.

--
John Popelish

Just trying to make the problem stand out in sharper relief.

I like the version that puts 3 lossy integrators (resistor across the cap) in a ring with an AGC to control amplitude. Spreads the tolerance problems around, too.

--
John Popelish

you must remember that a FET is a voltage device. you must make sure that the cutoff/pinch off volt and fully saturated volts are present at the gate. it appears that you may not be getting enough feed back voltage vs what your getting at the drain etc.. ect..

Second note. you may want to try a R to ground at the gate, this will help match the phasing angle and mite be your problem.

Lag or lead, these type of oscillator networks are crappy, due to the high signal loss. For cheapness they seem invariably built using one active device and that device has to supply lots and lots of gain and consequently supplies lots and lots of distortion. The lag network lowpass filtering benefit gets lost in the mess and at low frequencies also needs a high impedance load. 'Lytics are bad. I'd assumed you'd thrown in your biggest polylyprops etc.

2 of the above caps are polarised anyway. A 1Meg resistor from +9V to top of the 82k would lift it by .9V and polarise the remaining bottom left cap'. The circuit is a little dependant on transistor hfe but has a highish Rout, hence sensitive to external loading. I assumed a TUN hfe of 100 upwards,. The 27k in the emitter in conjunction with the 2Mohm bias is to fix a lowish emitter current of 100uA.(3V/27k) This services a balancing act between a high transistor input resistance and voltage gain enough to allow oscillation. The 100uA allows an internal 're' value to be developed of 25/.1ma =250 ohms. This 250ohms works with the 27k load resistor to give a potential voltage gain of 27k/250 =100X. This gain excess is needed to guarantee overcoming ladder network losses and component variations (say 20-30X). As the ladder network is needing high value resistors, then the transistor Rin is made to equal the value of the last resistance in the network. (The 2Meg self bias, needs decoupling to stop the circuit acting like an inverting op-amp and forcing too low a gain, hence no oscillation). Transistor Rin will be 250ohms times the transistor hfe of (say)100, in // with the 1Meg bias resistor, giving an Rin of about 25k which mismatches the ladder network but results in a better network loss and the oscillator speeding up to a handy 0.1Hz.

It's all incidental of course as it's a damned Fet you're having trouble with :-) regards john

With the jfet, 10:1 resistance steps with 4 stages is feasible.

But phase-shift oscillators still suck.

John

I think that's what I'm gonna do. Add another RC section. Here's the schem so far, below.

When you say gain, I presume you mean over the three equal sections. In other words, over the usual loss of 29.

+9V | .-. | | 19k| | '-' | .------------------------------------o----o 0.1Hz | | 4Vpp | o-------o | .-. | | | | | | 4.3M .-. | | | 330k === | | +------o V out '-' GND | | | | '-' | | +|| | |- o---/\/\---o---/\/\----o--||--o--->| JFET MPF102 | | | || |- | 330k | 330k | 100u | | | | o----. | | | | | | | | .-. | --- 1.0u --- 1.0u --- 1.0u | | | + --- --- --- 3.3k| | --- 2 caps | | | See '-' --- 3200uF | | | note | | total === === === below === === GND GND GND GND GND

Note: A BAV21 diode is in series with the 3.3k to give another .55V drop, to put more negative bias on the gate. Total drop across both is about 1.45V.

I like the low pass version better than the high pass one, even if it does need an extra coupling cap and bias resistor.

That should have about 6 db more loop gain with the staged impedances I described earlier.

Say, 33k and 1 uf to 68k and .47 uf to 120k and .22 uf.

--
John Popelish

I meant that the overall plase-shifter output voltage (ie, at the gate) will be 0.25 of the input (at the drain), so the fet only needs a voltage gain of 4 to oscillate. That assumes the RCs don't load each other, so each R must be a lot bigger than the previous one; 5:1 or even 10:1 might be practical in 4 stages.

10K 100K 1M 10M

with correspondingly decreasing caps to keep all the time constants equal.

If it's a lag network, the first R (the 10K) can be the drain resistor itself, with the first C from drain to ground. Then three more R-C thingies (100K etc) back to the gate. That ought to oscillate.

John

10/10 for hanging in there!. Load resistance is about 5X too low. Found a MPF102 spice model. It works (1Hz), using an 18V supply, 100k load resistor and 5 diodes in series to get the drain current down to the 100uA area. (takes a while to startup :-) regrds john

Thanks for the clarification. In that case, I seem to agree with John Larkin, at least to the extent that the FET has a very high input impedance and the BJT middlin' low. I slept/drank throught the lead/lag network class, but I know impedance matching has a lot to do with it - as to whether you'd just use different component values, or series R parallel C, I'm not qualified, but it's a pretty reasonable guess that that's what distinguishes a "lead" network from "lag".

BTW, I just checked out AoE from the library - it rocks! And I think I could look up your circuit somewhere in the last couple of chapters that I've scanned. ;-) (that's scanned, as in "read lightly", not with a scanner.)

Cheers! Rich

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Wow. I just got thru watching the piece about Google on 60 Minutes. Took half of the hour. Like, they have some really great ideas. But I still won't *ever* use the search (or anything else) via text messaging on my cellphone. People don't realize that 10 cents for a message and reply is the most lucrative money machine for the wireless companies. It's a license to steal your money!

And this Aishwarya Rai, what a babe. There are 17,000 websites about her.

As of Sunday evening, Jan 3, 05, I added the fourth RC network. With four, the oscillations are longer, and last about 30 seconds but they are still damped out after that time. It's like this thing just does not want to sustain oscillations.

+9V | .-. | | 19k| | '-' | .----------------------------------------------o----o | | | o-------o | .-. | | | | | | 4.3M .-. | | | 330k === | | +------o V out '-' GND | | | | '-' | | +|| | |- o---/\/\---o---/\/\--o--/\/\----o---||--o--->| JFET MPF102 | | | | || |- | 330k | 330k | 330k | 10u | | | | | o----. | | | | | | | | | | .-. | --- 1.0u --- 1.0u --- 1.0u --- 1.0u | | | + --- --- --- --- 3.3k| | --- 2 caps | | | | See '-' --- 3200uF | | | | note | | total === === === === below === === GND GND GND GNF GND GND

Note: 2 BAV21 diodes are in series with the 3.3k to give another 1.2V drop, to put more negative bias on the gate. Total drop across all 3 is about 2 V.

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Latest version. Skip to bottom.

As of Sunday evening, Jan 3, 05, I added the fourth RC network. With four, the oscillations are longer, and last about 20 seconds but they are still damped out after that time. It's like this thing just does not want to sustain oscillations.

+9V | .-. | | 19k| | '-' | .----------------------------------------------o----o 0.1Hz | | 4Vpp | o-------o | .-. | | | | | | 4.3M .-. | | | 330k === | | +------o V out '-' GND | | | | '-' | | +|| | |- o---/\/\---o---/\/\--o--/\/\----o---||--o--->| JFET MPF102 | | | | || |- | 330k | 330k | 330k | 10u | | | | | o----. | | | | | | | | | | .-. | --- 1.0u --- 1.0u --- 1.0u --- 1.0u | | | + --- --- --- --- 3.3k| | --- 2 caps | | | | See '-' --- 3200uF | | | | note | | total === === === === below === === GND GND GND GNF GND GND

Note: 2 BAV21 diodes are in series with the 3.3k to give another 1.2V drop, to put more negative bias on the gate. Total drop across both is about

1.45V.

I'm gonna raise it in a few minutes. Trying for 22k to start.

load

100uA

Yeah, I noticed - and it takes a while to damp out. I think I'll try higher supply voltage to see what happens.

Thanks.

This not a dying ringing oscillation as such... something DC is happening. Either the source cap is charging up or the gate is pumping itself negative. Probably the source cap.

Dump the diodes and fiddle with the source resistor.

John

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I thought about using a 2N7000, but I wanted to 'play' with the bag of JFETs that I got. I remember back in the mid '60s a friend and I built a 'compander' that used lamps and photocells and some FETs. It didn't work, and I had to go thru and adjust all the values of the bias resistors to get the FETs to be in their linear region. It was all because of the wide variation in JFETs' Vgs, which in the case of the MPF102 can be anywhere from a half volt to 7.5V. That's a 15:1 variation!

I finally got the damn thing to sustain oscillations. See schem below.

out

I finally got this version to oscillate with the values below.

+9V | .-. | | 33k| | '-' | .----------------------------------------------o | | | o-------o | .-. | | | | | | 4.3M .-. | | | 330k === | | +------o V out '-' GND | | | | '-' | | +|| | |- o---/\/\---o---/\/\--o--/\/\----o---||--o--->| JFET MPF102 | | | | || |- | 330k | 330k | 330k | 10u | | | | | o----. | | | | | | | | | | .-. | --- 1.0u --- 1.0u --- 1.0u --- 1.0u | | | + --- --- --- --- 3.3k| | --- 2 caps | | | | See '-' --- 3200uF | | | | note | | total === === === === below === === GND GND GND GNF GND GND

Note: 2 BAV21 diodes are in series with the 3.3k to give another 1.2V drop, to put more negative bias on the gate. Total drop across both is about

1.45V.

[snip]

I finally got it to sustain oscillation with the following values. The two diodes in series with the source are just to give a constant voltage drop. I could chang them to a single resistor. But at this low freq, I thought that the 3200 uF byp caps might not be enough, so using diodes would make it easier to bypass. With the 33k drain load resistor, it's finally oscillating. It just takes a couple minuites to atart up, that's all.

I went to 22k then 27k load resistor, and it still wouldn't oscillate. Finally the 33k did the trick.

+9V | .-. | | 33k| | '-' | .----------------------------------------------o----o Vout | | | o-------o | .-. | | | | | | 4.3M .-. | | | 330k === | | +------o V out '-' GND | | | | '-' | | +|| | |- o---/\/\---o---/\/\--o--/\/\----o---||--o--->| JFET MPF102 | | | | || |- | 330k | 330k | 330k | 10u | | | | | o----. | | | | | | | | | | .-. | --- 1.0u --- 1.0u --- 1.0u --- 1.0u | | | + --- --- --- --- 3.3k| | --- 2 caps | | | | See '-' --- 3200uF | | | | note | | total === === === === below === === GND GND GND GNF GND GND

Note: 2 BAV21 diodes are in series with the 3.3k to give another 1.2V drop, to put more negative bias on the gate. Total drop across both is about

1.45V.

T00bz r t3h pwn ;D

Tim

-- "I've got more trophies than Wayne Gretsky and the Pope combined!" - Homer Simpson Website @

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