Latest threads in Field-Programmable Gate Arrays

problem with programming avnet edk board over LPT

hi all, i am using a development board from Avnet featuring a Spartan 3. I am trying to download a bitstream to the boa...

7 21yrs

karagiozhs

7 21yrs karagiozhs

DCM question

I have a question that is more theoretical than practical: The DCM uses the feedback loop so that it can create a 360 (...

4 21yrs

zoinks

4 21yrs zoinks

ISE 7.1 on Linux, ngdbuild failed without error

I am using ISE 7.1 on linux Redhat Enterprise 3.0, During translate phase of design, ngdbuild fails, but there is no er...

0 21yrs

ash.ok7

0 21yrs ash.ok7

Version Control Software

I've just started looking into getting our VHDL code into some sort of version control tool, and would like to get some...

16 21yrs

neilla

16 21yrs neilla

flash on P160 Module

Hi All, I want to use the flash on the P160 module, but I have to set the OPB EMC(External Memory Controller) for flash...

0 21yrs

lnzhao

0 21yrs lnzhao

Xilinx ML403

Hello group, Can anyone tell me about the ML403 kit that Xilinx now advertises on there home page? Specifically, is the...

8 21yrs

bradsmallridge

8 21yrs bradsmallridge

SDRAM HOW?

Hi.. I am trying to use SDRAM (not chip but SDRAM as i PCs)of micron in one of my projects (Gamin Console).IActually i...

4 21yrs

fahadislam2002

4 21yrs fahadislam2002

Small (OEM-)Memory Modules (SRAM/FLASH/DRAM)

Hello, I'm looking for small memory modules with - SRAMs (normal and fast) - FLASH - DRAMs which I want to use for test...

3 21yrs

WeikEngOff

3 21yrs WeikEngOff

Starbridge Hypercomputer & Viva

I heard quite a lot about the Viva development environment last week at the MAPLD 2005 conference in Washington DC. A l...

1 21yrs

robin.bruce

1 21yrs robin.bruce

Xilinx V2Pro & SATA hard disk

Hi all, Does anyone has implemented a SATA link on Xilinx V2Pro to connect to a hard disk drive ? Indeed, we have the X...

3 21yrs

nospam

3 21yrs nospam

ISE 7.1 service packs

Hi all, I just received a copy of ISE7.1, I removed the old 6.3 and installed it. I also installed the service pack 1 I...

1 21yrs

nemesis2001

1 21yrs nemesis2001

HAL fuse map organization issue

I'm beginning to question the organization of the fuse map in a HAL. It doesn't seem to be related to the datasheets. I...

1 21yrs

grant

1 21yrs grant

Matched Filter

I'm designing a digital QPSK transmitter & receiver. At the transmitter, i'm using xilinx spartan3smb1500 to generate t...

0 21yrs

faaizal

0 21yrs faaizal

PCI configuration questions.

Hi folks, I am starting to implement a simple PCI core using Spartan-II. I have already implemented the basic read and...

4 21yrs

heibear

4 21yrs heibear

IP Protection of code block in Xilinx FPGA?

I have an FPGA design where the VHDL source code is a deliverable item to the customer. One of the blocks in the FPGA m...

4 21yrs

urbpublic

4 21yrs urbpublic

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