Hi,
I vaguely recall reading papers that described an automated pipelining technique that could take an existing synchronous design and turn it into a N-way hyperthreaded design by replacing all the flip flops with N chained flip flops.
I'd like to look at those papers again, but I can't remember what it was called, and my google-fu is weak.
Any ideas?
Thanks, Allan
I think "C-Slow retiming" is the academic term for the transformation.
The earliest moniker I've heard as applied to a processor is "barrel processor" [CDC], with something like "N-way sequential multithreaded" being the modern terminology.
IIRC, Tobias at edaptix had written some articles about his automated implementation of the technique on the late Programmable Planet website, see:
-Brian
Perhaps PicoPIPE as used(patented) by Archronix?
Hans
C-Slow it was. Thanks very much.
Regards, Allan
I've seen it termed 'System Hyper Pipelining'.
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