booting a large V4 PPC program with a minimum of on chip bram

I am trying to boot the PPC with a minimum of block ram, since I want to save that for my own hardware peripherals. My idea is to take the smallest amount of on chip memory (4K of isocm seems to be the minimum - why not 2K I wonder) and hold a small assembly language program that will copy my real program from external flash into DDR space, initialize the data sections and go. All the boot examples I have seen seem to use xil_kernel and take up an obscene amount of on chip memory. Does anyone know of a better way? I looked at the ultra-controller design that runs only from cache, but it seems the only way to load the cache is with XMD which is no good for stand-alone embedded booting.

thanks, Jeff

Reply to
Jeff Cunningham
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The ppc is going to start at 0xfffffffc. What you boot from depends on what you place at that memory location. You should be able to boot from flash, provided it's visible from your instruction PLB bus. All you need to do it point the stack somewhere into DDR and then you can write the rest in C, provided you avoid global data:

boot() { back: /* assuming your DDR starts at 0, a small stack */ __asm ("li 1,1024"); yourfunc(); /* put this function at the end of your file and this will be the * last instruction, which will go at 0xfffffffc and run first! */ goto back; }

Just put that at the end of your file, compile it to a .o, then use `objcopy -O binary boot.o boot'. Then pad the file `boot' so that you can flash it at the end of your flash space. If you start getting fancy you'll eventually need a custom link script and more magic to relocate the code, but if you just zero some memory and copy some stuff around before jumping into it, you'll be fine.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

Thanks for replying Ben. In my case I'm trying to save fabric by not having any PLB-OPB-flash path (I didn't see any direct PLB to flash IP, and I'm leery of making my own PLB slave). So the flash is not memory mapped. Instead, I made a DCR peripheral that can do simple programmed-register type access of the flash. So my tiny assembly language boot program would use this peripheral to read the flash and fill the ddr.

I guess the choice is to either make a PLB slave that can access the flash, or sacrifice two brams. A nice thing about the DCR reading of the flash is that I can also do a CRC check of the data to make sure it is not corrupted before trying to run it. So I can have my normal application code, which can be updated by the user, plus a backup copy to fall back on if the primary application code gets corrupted during user updating, and have this all happen automatically during bootup.

-Jeff

Reply to
Jeff Cunningham

There's one more option. You can implement a custom ISOCM slave to interface a tiny COREGEN ROM with your loader code. It should be do- able with

Reply to
jetmarc

oooh, I like that idea. Maybe I wouldn't even need to implement a custom controller. If I make a custom ROM that acts like a block ram, with the

1st 16 locations aliased throughout the bram space that should do it.
Reply to
Jeff Cunningham

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