I'm using a Cyclone II with 1.2V core. The 1.2V regulator has an open drain "power good" signal and a cap to delay that after startup.
It looks like I could hook this to either nSTATUS or nCONFIG to delay FPGA configuration. The only difference I can see is that nSTATUS is meant for daisy chaining FPGAs and does not appear to be tested after configuration unless nCONFIG is first pulled low.
Looking at the Configuration Cycle State Machine (p1-5, figure 1-2 in the configuration handbook) it looks like the chip itself has a 'power supply not stable' test, and it may not be necessary to hook up PWRGD at all.
What's the best practice here?