Just a stupid question:
I need to implement something in high speed so I have to use RLOC_ORIGIN statement as some experts suggested. However, I couldn't find any information regarding to the "which CLB (x?y?) associate with which output pin". Does anyone know which Xilinx document to look at for the "addresses" and phyiscal location of CLBs for certain FPGA? ( I am doing design with Spartan 3 and Virtex 2 pro).