Xilinx PCI Express - Am I starting too low?

Hello,

I have used the Xilinx LogiCore Integrated Block for PCI Expres several times in the past. On those occasions I have hacked into the autogenerated example design to bring a standard parallel interface up to the top level for access to registers and block ram. This work has always been for prototyping and was not really production firmware. Working this way the PCI Express performance is really low because the Logicore IP does not support burst transfers or DMA. The software engineer hacks the linux driver to prevent any PCI Express accesses of greater than one word so we don't get bus errors.

I just genenerated a version 2.4 AXI4 compatible PCIe core for V6 using ISE 13.3 and I see the design still supports only single word accesses.

Now we are dong a production design using PCIe and I would like to get the full performance of the interface. In particular I must support burst transfers. Ideally I will also provide DMA logic.

Can anyone advise me where to start in order to get where I want to go?

Am I starting too low using the Xilinx Logicore design?

Does Xilinx provide a better core or reference design with burst transfer and DMA?

Any advice is greatly appreciated.

Pedro