Xilinx ISE 8.2

bgshea · 2007-01-22T18:17:29+00:00

I'm looking for POSITIVE feedback on Xilinx ISE. Yes i realize it hasit problems, but It's free. So, I've been looking round the WWW to findsome tips on what type of system (Windows, Linux, Intel x86 or EM86_64,AMD, etc) that might result in better software preformace.Also, considering the effects of the Java RTE.I would like to post these suggestions to a page on my site, but ifthis turns in to a flaming war, i will cease and go elsewhere.So, here is what I have, and my problems:I have a Windows XP based system with Xilinx 8.2.03 and Chip Scope Pro.AMD Athlon 64 3000+1GB DDR RAMHere are my issues:During the hardware validation process, i tend to make many smallchanges to several projects (i have 4 FPGAs in my system on seperatecards all being developed in parallel), esp to CSP which requires manyrebuilds and downloads. Since I'm working with Spartan 2 I cannot takeadvantage of Partitioned designs. After about 10 or so builds anddownloads my physical ram usage is 1.5GB and my system is swapppingconsistanly. Reviewing the windows resource usage, it shows only about150MB for _PN.exe, however, closing the ISE will free up nearly 1GB ofram.So, is this a Java issue, should I upgrade my JRE, or does ISE use it'sown JRE?Is it a System issue, should I switch to a Linux based environment? orDrop back to an older version of Windows such as w2k.Could it be a design flaw in my Design. I use a TLD with only IO Logicand Global Clock buffers, all modules/sub modules contain relatedfunctional logic. TLD only provides wired interconnect between modules,no tri-state buses. Modules register inputs and outputs on clock edges.I haved contacted Xilinx on this matter, and will leave it at that tostay imparital.Thanks for any feedback.Brian

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Andreas Ehliar 19 years ago

Hi, I wrote some Makefiles that we use in a course here. The entire lab skeleton is actually available for download but I have uploaded just the Makefiles to my homepage if you are interested:

formatting link

It is not perfect but it works ok for me and most students in the course seem to think so as well :) They have been tested in both Linux and cygwin.

I wrote the Makefiles for the following reasons:

Since they are text based, revision control is easy
We can avoid the (for now) unstable Project Navigator
Building a project will not spew lots of temporary files in the project directory. (They will end up in the synthdir directory.)

The Makefile has been tested with ISE 8.1 and 8.2.

I also have a small shell script which I use to build small projects where I haven't bothered to create a Makefile. That is also available on the web page. It is heavily inspired by the Makefile mentioned above.

Some things which would be nice to be able to handle:

VHDL libraries (not everything should end up in work)
Don't recompile all files when starting a simulation target
Mixed VHDL/Verilog in the Makefiles

Tips and tricks for these Makefiles will be gratefully received :) I know that they are a bit ugly at the moment.

/Andreas

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Martin Thompson 19 years ago

Interesting - could you say any more about what makes vhdl-mode so bad? My experience has been more of people thinking Emacs sucks, but they wish their editor did all that vhdl-mode does!

Thanks, Martin

martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html

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Daniel O'Connor 19 years ago

Sure that's VHDL mode? I can't see anything in the docs about simulation..

Hmm, it looks very interesting but I use Verilog :)

I need to know the commands.. I am software guy and all the "compile" steps are confusing :)

Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C

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Martin Thompson 19 years ago

Yep, definitely... It's in the compilation section as none of it is simulation specific, I just target the Modelsim compiler.

Ahh, in that case, sorry, you're out of luck I think. Unless verilog-mode is as far on as vhdl-mode...

See my makefile I posted elsewhere on this thread...

Cheers, Martin

martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html

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Eric Smith 19 years ago

Completion/templates get in the way of my typing. I know what I want to write, but if the editor starts inserting stuff for me, I have to think about the typing much more, so it slows me way down.

Eric

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Daniel O'Connor 19 years ago

OK.

Apparently not :) It is still very useful though.

Yeah I found a few links, thanks!

Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C

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Martin Thompson 19 years ago

Ahh, yes I can understand that - I had a similar problem except that when I started, I was very rusty at VHDL, so it helped. I'm now so used to the templates that inserting a new process becomes: procthen type in s docunmmentation comment if I feel like it and prod enter a few times to get rid of any extraneous prompts.

That sounds like a right palaver, but honest, it helps me :-)

I wrote a new piece of code the other day and it compiled first time, because the templates and tab-completion of variables/signals meant my customarily inaccurate typing hadn't caused any syntactical problems.

Cheers, Martin

martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html

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