Hi everyone,
i am trying to connect a design of mine to the OCM interface of a Power PC on a virtex II Pro FPAG. I need sometimes to stall the Power PC for several clock cycles until my design fetches and deliver the correct data to the PPC. I am trying to stall the processor by using a combination of two specific signals (CPMC405CPUCLKEN and DBGC405DEBUGHALT). While this approach works satisfactory, there are some cases (in simulation)where after a stall the processor enters an undefined state forcing all of its signals to xxx. Do you have any idea why this happens? Have anyone ever tried to stall the Power PC?
Thanks...