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SPARTAN-IIE -> LVCMOS18

Hi experts,

In a new board design I have to build a generic IO PORT. This generic IO port will be connected to an connector (20-pin header).

The output drive voltage will be LVCMOS18 for some applications and LVTTL for some others applications.

My question is : Did I need to specifiy LVCMOS18 and LVTTL in the .ucf file and create two .bit files (one for LVCMOS18 and one for LVTTL) ? OR could I only create one .bit and work with the VCCO only ?

Same questions for Coolrunner-II

Thanks Laurent Gauch

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Reply to
Amontec, Laurent Gauch
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Hi Laurent,

Regarding CoolRunner-II, make sure that you configure the device for LVTTL or LVCMOS18 accordingly.

You can either use the .ucf file to specify the constraint or use the GUI to do it.

The LVTTL and LVCMOS18 settings affect the way that the CoolRunner-II IOs are configured. No real damage will occur if you set LVCMOS18 and tie Vccio to 3.3V (or vice versa). However, your rise/fall times and drive strength will get affected if you have the wrong settings...

Hope that helps! Mark

Am> Hi experts,

Reply to
Mark Ng

Hi Mark,

Many thanks for your comments.

Is that the same for Spartan-IIE ?

My goal is to provide an new version of my Chameleon POD but using USB2.0 and a colrunner or SPARTAN-IIE. The first objective of this new Chameleon based USB2.0 will be to build an JTAG interface accelarator.

Actually, JTAG can be 3.3V or 2.5V (will be 1.8V in future), so I ask me if there are a sense to do the voltage level converter directly with the VCCO. The VCCO will be drived by the user board target.

What do you think, is that acceptable?

I will do some tests next week concerning rise/fall times and drive strength when configuring the FPGA with LVTTL and driving the VCCO to down 1.8V

Best regards, Laurent

Mark Ng wrote:

Reply to
Amontec, Laurent Gauch

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