But if I use a two stage FF synchronizer for NXT_raw and my answer byte to NXT_Q is also synchronous that is registered I would be one 120MHz clock cycle too late (?)
Rgds Andr=E9
But if I use a two stage FF synchronizer for NXT_raw and my answer byte to NXT_Q is also synchronous that is registered I would be one 120MHz clock cycle too late (?)
Rgds Andr=E9
So, Andre...
What's up? How are things going? Are you successful so far?
VRgds André
Hi Vladislav,
I am waiting for the new board release.
When I can test it I will give account.
Rgds Andr=E9
Hi, I have one more question about placing registers:
If I have a bidirectional bus do I have to make the decision whether to place the "input"bus into input registers (for better tSU/tH) or whether to place the "output" bus into output registers (for better tCO) ? Or is there some option for both ?
I can imagine of situations when using input AND output registers could be necessary,
Thank you for your answers.
Rgds
You can register both, but the target silicon will dictate whether you get the performance you want.
For example, the Flex10K architecture only has one flop in the IO cell, so the other has to go in teh fabric. Altera claim this is mitigated by the fast local interconnect, but I could never get the timing to be reliable over all temp/voltage/process for a 100MHz SDRAM interface. I either met tsu because the input register was packed in the IO cell, or tco, because the output one was. I could never persuade the software to place the "other" register close enough in the fabric to meet timing.
Still, it worked in the environment we needed it to in the end - so long as it didn't get too hot.
Cheers, Martin
-- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt
Registers are inferred from the code, only placement can be constrained. If I use both input and output registers then I usually only need Fmax as a constraint and I can let the place and route pick the register location. Without an input register, timing constraints are more complicated.
-- Mike Treseler
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