Hi,
I am working on a design where there are different components coded by different people. I am integrating all of these into a single top module.
Different components have transitions on different edges of the clock.For eg: a FIFO in the design waits for the negative edge of the clock whereas another component waits for the positive edge of the clock...
My question is...will it lead to synthesis problems if I make the code work keeping the different clock transitions or should I make all of them(including the subcomponents) transition on the same edge of the clock..
I am synthesizing to Virtex XC2V 4000 FPGA and am planning to download the bitstream and show a working proof
Thanks, Hardware Engineer