using both edges of clocks in a design - effects on synthesis

Followup to: By author: snipped-for-privacy@gmail.com (hardwareengineer) In newsgroup: comp.arch.fpga

Depends on the FPGA you're synthesizing to. Most current FPGAs can clock any particular register either on the positive edge or on the negative edge, but not both.

I have not had any problems having some elements clock on the positive edge and some on the negative edge, however, and the timing tools seem to deal with it fine as well.

-hpa

Sounds like you had some very poor project management. A top down design phase would have spec'd all the interfaces so that this would not be an issue.

The real question is, did they do their designs knowing the clock phasing of the other components? If a pos edge register feeds a neg edge reg (or vice versa), you will only have half a clock cycle for the signals to run through the logic and routing and meet the setup time of the destination register. Otherwise the synthesis software will do exactly what you want and give you logic clocked on what ever edge you spec.

I recently received such design too, with a FIFO being clocked on the negative edge and the rest on the positive edge. It synthesizes and works fine, but Quartus says it can't achieve the timing goals, whatever speed you enter. But this is a matter of setting up the timing constaints properly I've been told; still have to check that out.

Jeroen