Using an FPGA to drive the 80386 CPU on a real motherboard

That is a very naive ideology. If you abolish patents and make all ideas free, there is much less reason to invent. Most people are motivated by profit which patents potentially provide. I expect you are going to talk about designing for the glory of God. However I would point to the design you are doing and how it will benefit virtually no one other than yourself. If ARM were devoted to the type of chips they were designing in the 90's, would that be a good thing?
Patents are no more oppression than laws to prevent the theft of crops you raise or goods you make. That's why they call it Intellectual Property.
Perhaps you are a pure socialist who believes no one should own property, that it should belong to everyone.
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Rick
Reply to
rickman
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Just to note that there's a free descendent of Protel which is called CircuitMaker:
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I haven't used it, but I use its commercial sister Altium which is pretty nice. The difference with CircuitMaker is your boards have to be public, there is no way to keep them private. So it's no good for commercial work, but that limitation is not a problem for an open source project.
(It's also not open source, but my experience is the proprietary tools are generally several steps above the open source tools - depending on board complexity, going with proprietary tools can be a necessary evil to get work done. It also relies on an internet connection)
Theo
Reply to
Theo Markettos
RISC-V is an architecture, and various chips have been produced. It's also getting embedded in other products (eg as a tiny part of some other SoC).
My colleagues at LowRISC:
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are working on a fully open-source SoC based on the RISC-V architecture - ie open source at the Verilog design level, including peripheral IP. They still face many challenges, including the need to use proprietary ASIC tools and hard macros (eg memory generators). Their initial run is aimed for a multi-platform wafer service.
There is an argument that the i386 has the largest software stack, so an i386 will have the most compatibility. However, that is changing. The Linux kernel doesn't support the i386 any more. Many binaries end up using MMX, SSE and so on, so won't work on an i386. Other operating systems are more platform agnostic (eg Android runs on ARM, x86, MIPS and others).
Maybe that doesn't matter to you, but the question is not just what is the best choice now, but what might be when the you hope to be finished.
One useful feature of RISC-V is they have ISA subsets: the base RV32I subset is quite small, and then features like 64 bit, floating point, etc are extra. That means the instruction requirements of software are made explicit.
ARMv2 (ARM with 26 bit addressing) is now out of patent, so it's possible to implement it licence-free, and it has been:
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That is one thing in favour of the i386 against newer architectures: it is now out of patent, so Intel can't sue you for making one.
We've also designed our own 64-bit CPUs, with our own ISA extensions. Multicore and cache coherency were a significant effort, likewise we spend a lot of effort on testing.
Software is indeed a lot of work, though using the maximum of pre-existing software helps.
This is the tricky question about the 'homebrew silicon fab' question.
I think there's an interesting space for the 'artisanal semiconductor fab', that makes old chips relatively cheaply and allows users to get closer to the process. Some universities have that kind of facility, but often not intended for even medium volume manufacturing. But a general democratisation of fab technology could be an interesting space.
You'd think that using new techniques on an old process would make life easier, just like people can make marble sculpture with CNC machines instead of hammers.
What hits you, however, is lack of Moore's law. Let's say you have a 3 micron fab. You might only have two metal layers. You just can't get many transistors on that chip, and you can't wire them very well. The tools aren't optimised for that kind of environment, and will waste space trying to deal with layer limitations. You also can't fit much memory, and you can't deal with modern interfaces (no USB for you) or modern off-chip DRAM.
You'd end up with 1970s style hand design, albeit with a fancy GUI rather than plastic tapes, connected to 1970s peripherals.
Maybe you can deal with some of those by careful choice of off-chip components (eg everything is SRAM, not DDR4) and others by die stacking a commodity small-process interface die on top of your large-process die.
Maybe the 'artisanal' producer makes the coarse-grained silicon interposer, and then stacks commodity dice from other vendors on it - like hobbyists make and assemble PCBs today. It does, however, require an ecosystem set up for that.
Theo
Reply to
Theo Markettos
I don't think the restriction was ever patent based. It was a matter of microcode copyright. That is why AMD had to use cleanrooms to generate a spec for all subsequent CPUs they desired to copy. That gets around copyright. So the 386 doesn't have an advantage over other x86 processors in terms of IP protection while it does have an advantage over patent protected designs.
I would like to see an open source effort for FPGAs. I think the big roadblock would be the fab, but maybe it's more of a seed money issue since wafers can be bought for a reasonable price. A *very* small startup created an array CPU on a shoestring a few years ago. They have run a second batch of chips, so they must be selling them to someone. It's just a question of proving a market exists and coming up with the startup funding.
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Rick
Reply to
rickman
Well much to my surprise, I was watching CPU-related videos today and I came across this video:
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Beginning around 4:22 it shows the very type of board I was looking to create to plug in to an existing 80386 system and monitor its signals.
Does anyone have one of these types boards on their shelf from back in the day?
Best regards, Rick C. Hodgin
Reply to
Rick C. Hodgin
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But I doubt that a complete 386 will fit into a FPGA.
Reply to
Herbert Kleebauer
How exciting! :-)
A man named Aleksander Osman has created a full 486SX CPU in an Altera FPGA (Terasic DE2-115 only, and it does not have an FPU):
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It is comprised of:
Unit Cells M9K ---------------- ----- --- ao486SX CPU 36517 47 floppy 1514 2 hdd 2071 17 nios2 1056 3 onchip for nios2 0 32 pc_dma 848 0 pic 388 0 pit 667 0 ps2 742 2 rtc 783 1 sound 37131 29 vga 2534 260 ------------------------------- Total: 84,251 393
After compiling with Quartus II:
-----[ Start ]---- Fitter Status : Successful - Sun Mar 30 21:00:13 2014 Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : soc Top-level Entity Name : soc Family : Cyclone IV E Device : EP4CE115F29C7 Timing Models : Final Total logic elements : 91,256 / 114,480 ( 80 % ) Total combinational functions : 86,811 / 114,480 ( 76 % ) Dedicated logic registers : 26,746 / 114,480 ( 23 % ) Total registers : 26865 Total pins : 108 / 529 ( 20 % ) Total virtual pins : 0 Total memory bits : 2,993,408 / 3,981,312 ( 75 % ) Embedded Multiplier 9-bit elements : 44 / 532 ( 8 % ) Total PLLs : 1 / 4 ( 25 % ) -----[ End ]----
Runs at 39 MHz. Boots and runs:
Microsoft MS-DOS version 6.22 Microsoft Windows for Workgroups 3.11 Microsoft Windows 95 Linux 3.13.1
Best regards, Rick C. Hodgin
Reply to
Rick C. Hodgin
I have been in contact with Amanda from their sales department. They are unwilling to sell me a single board with hardware interface because I am not a company, and do not / will not have volume throughput. However, I have also found out they sell a Soft x86 IP Core which is for Altera FPGAs, so I am finding out if they will sell me a copy of that core or not, and how much it costs.
Now, off to pray... :-)
Best regards, Rick C. Hodgin
Reply to
Rick C. Hodgin
Why don't you tell them that you maybe will order 10k boards, but first you need a free demo board.
That doesn't help. Don't pray but lie if you want a board.
Reply to
Herbert Kleebauer
It would be easy. But, it's not the call of God. It is the call of the enemy tempting people away from God for the immediate thing. It's how sin works (immediate satiation, gratification, without regard to what the act means in the grander picture).
If it's meant to be, it's meant to be. If not, then I'm content to do a ground-up authoring of the entire ISA.
I'm only interested in having the existing ISA for a baseline, and to then test out extensions including a 40-bit extension, and the use of John Gustafson's unums instead of IEEE-754 floating point formats.
It may require a ground-up authoring anyway.
Best regards, Rick C. Hodgin
Reply to
Rick C. Hodgin
Sorry for the long latency guys, I don't have much time in the day for myself, so Usenet often suffers. :)
I find difficulty in producing a design that is simultaneously low- latency, high speed and feature-full. To obtain low latency, you really can't use registers as much as you would like, and instead have to shift a lot of the logic into gates (pure asynchronous logic). However, if you do that, you quickly add up a too long chain of gates that can not be run at high clock rates. Finally, if you get both of these, you probably won't have enough wiggle room left over for features.
Right now, with what I'm currently working on, I have a blessing in that I don't have to run the circuit very fast so I can get away with three- gate deep logic, maybe even four gate deep. But if I were going for break- neck speeds, I would be constrained to logic two LUT4 gates deep. Only so many features can be crammed into a design made with that. :)
I suppose you can parameterize the data size, and later change the definition of the parameter to suit.
The problem - for me - is the underlying result which still needs to fit in the real world. This may have something to do with the way I cram as much "stuff" into a chip as I can. It was only here that I learned you should consider your chip "full" when it start reaching 80% utilization. For me, over 95% is common.
Adding a single bit to a round number can throw the synthesis results way out of optimum. Adding one more can make the gate chain too long to fit into a clock cycle. Changing the clock period can be impossible because the design could have several other interlocking clocks. And on and on.
For example - I discovered that the synthesis tool I used (Lattices synthesizer) would produce a sub-optimal result if a unit - say a module - had even a single odd-sized register. Changing the register sizes to even numbers makes synthesis much better, even if it does throw away a bit.
A device whose design can fit in my head, that is transparent and serviceable on all levels, free(-as-in-freedom), secure and usable for real-world tasks. I should probably put "usable" at the top of the list. :)
Right now, that would mean a FPGA-implemented FOSH SoC that is self- contained. That means, which can regenerate the images and binaries of itself, by itself (so you don't need a second computer for that).
Reply to
Aleksandar Kuktin
Maybe I don't know what you mean by fast and not fast. Got some numbers?
Not just parameters, but the instruction format doesn't care. Literals are built up in 7 bit chunks from an 8 bit instruction or 8 bit chunks with a 9 bit instruction since many FPGAs have memory and multipliers 9 bit wide multiples. The data path has no restrictions on width.
I'm not sure how that related to CPU designs. It has to be a very complex CPU to not fit in any but the very smallest FPGAs. My CPU was about 600 LUTs which is not uncommon for MISC.
Now you are way outside the issues of CPU design. Now you are in the design of your application.
What was suboptimal about a register? What sort of unit?
I thought there was already a CPU design like that. RISC-V Does that not fit your description? Check out this page for ideas...
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Rick C
Reply to
rickman
Amanda contacted me today, and said the cost of obtaining their soft x86 IP core, which is comprised of an Altera compatible project files, and associated logic for the i386 CPU, would be $250,000 and up, and would have a lead time of three to six months.
I wanted to find out if you think this is a valid quote or not? (Given the fact that open source x86 cores capable of booting Windows exist):
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Best regards, Rick C. Hodgin
Reply to
Rick C. Hodgin
I had asked them in email if they'd ever designed an 80386 core or not, and if the product had a proven track use record.
I received a reply from an application engineer at Force Technologies. He reported they have not yet designed an 80386, but only an 80186 and 80286.
I have replied that I intend to write an 80386 compatible core using my Logician tool, which will compile down to Verilog and can be used in an Altera FPGA project file. I have offered to give them a free IP license once it is completed so they can have the product, and possibly pass along savings to other would-be customers.
Best regards, Rick C. Hodgin
Reply to
Rick C. Hodgin
I have no reason to doubt that it is a valid quote.
Kevin
Reply to
KJ
I have little experience with the price of FPGA IP cores, but given the types of prices for commonly used but much simpler cores such as fast memory controllers or Ethernet devices, this sounds like a bargain. We are talking about a very complex core with a very small customer base to spread development costs, customised for your use, with documentation, support, testing, and everything else involved in a serious and professional core.
The only surprising thing here is that they have given you permission to publish this pricing information publicly on the net - usually these sorts of things are confidential because they can vary significantly between customers according to the exact requirements. If they wanted their pricing to be public, they would have published figures on their website.
Reply to
David Brown
The type and manner of seeds we sow reap their harvest in due season, David. I advise that you quickly change seeds.
Best regards, Rick C. Hodgin
Reply to
Rick C. Hodgin
What on earth does that mean? If you trying to say that you did not like something I wrote, then it would make a lot more sense to quote the part you didn't like, and then explain why you didn't like it. If I have written something that is incorrect, or written in a way that is causing upset or insult, then I would rather hear the actual complaint. That way I can either justify or defend my viewpoint, or correct it, or apologise, as appropriate. Suggesting that I "change my seeds" doesn't help anyone. I can only assume that it is some weird religious reference, and we all know how little respect anyone has for your peculiar ideas in that area.
At a guess, your issue is my point that companies that provide individual quotations tailored for individual customers, rather than publicly viewable standardised price lists, prefer to keep these quotations private. This is common practice - though I fully understand if you don't like it. In particular, if the quotation is restricted as confidential information, you cannot do, as you did, publish it and ask for opinions. But it is also quite possible - if surprising - that this supplier does not consider the quotation to be privileged information and are happy to see it published. My comment is therefore to encourage you to check the situation, and be sure you are not breaking any agreements or contracts with what you post, as that would surely jeopardise your relationships with this company.
Reply to
David Brown
Have you read the New Testament as an adult? Have you considered the possibility that you may be on the wrong path in life (not with your career or worldly things, but with eternal things)?
There are some questions you need to ask yourself, and seek answers on. If you're willing to do this, then you will inherently know what I mean. But if you are unwilling, you will never understand anything I write toward those ends.
----- David, you're an extremely knowledgeable man. Don't miss out on this teaching. Learn more than you know today. It will benefit all areas of your life.
Best regards, Rick C. Hodgin
Reply to
Rick C. Hodgin
I disagree with your third point.
Reply to
Tom Gardner

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