I am a graduate student and would like to implement the SATA I Host Controller Link and Transport layers in an FPGA for my Project. I am just starting on the RTL coding but would like to plan ahead for the verification of my RTL design. Can anyone guide me towards how I could write a testbench to verify my design and how doable is it. Are there any freely available Simulation testbenches for SATA I in which I can plug in my RTL code for verification. Let me know if there is a more apprpriate forum to address this question. Thanks.
Are the SerDes in SATA significantly different from PCI Express and InfiniBand?, both of which work fine with RocketIO. SATA is a lower clock rate than PCI Express and InfiniBand but I would have thought the logic levels would have been the same.
RocketIO can not do PCIe or SATA fully compliant to the specs without special external "tweaking" IC's and have possible problems even with such circuitry being used.
Problems are the initial CDR lock range and "Electrical Idle" Vdiff voltage.
Workarounds are for Serial ATA OOB transmit idle
1) series resistors and FET shunt Xilinx solutions
2) can be done with no circuitry by using POWERDOWN and 2 MGTs per channel (my solution verified in FPGA)
Workaround for CDR lock
1) SATA - not known !
2) PCIe - external high quality low jitter multiply by 1.25 PLL
Those workarounds are REQUIRED for compliance!
I think RocketIO has also problems with PCIe TxElecIdle and recovery time, but I have not tested that with real silicon and no-one has so far confirmed this problem (except that I think it is a problem)
PCIe requires TxElecIdle Vdiff to be less than 20mV and recovery to normal operation less than 20UI, thats not doable with rocketIO ASFAIK (not without similar to the SATA OOB Transmit workaround)
I dont know about the Infiniband.
It wonders me that you that rocketIO works fine with SATA and PCIe - it does not at least not without the tricks. Sure as per SERDES there are no problems getting SATA packets received with rocketio isnt that big problem, but getting the system compliant to the spec is.
PS I would be glad if I would be wrong with the statements here!
I am implementing only the link and transport layers as a RTL coding/FPGA Design project. So I guess I am interested in only a theoretical testbench to verify this. When researching the project it seemed that it would be a really difficult task to implement the Physical layer or would require high end FPGAs, so decided against it.
Any Ideas on how I could verify just the link and transport layers in Simulation - what kind of a testbench would i require.
If possible I would also like to program the design on to a low cost fpga board - if I do this is there any way I can verify the functionality on the board without additional hardware (Couldnt find any stand alone physical layer chips).
I have some Verilog / FPGA design experience but new to SATA and have no idea how I am going to verify my design.