Strange peaks on integrated POL module

The periodic appearance could be scope aliasing. Only some samples see the peak.

If you trigger on a lower peak voltage, for a single switching cycle, do you still see multiple amplitudes (between 5V and 6V)?

RL

The blue signal is the switch node, and in fact the periodic signal is 250kHz

I have checked, no such current load comes from the load

Also the PDN measurement shows no ugly peaks in that range

Good point

I have checked that, triggering on the peaks. It is indeed there. Zooming out just to find the beat frequency

Digikey has it, $2.07 at 1K. Not bad... if it's reliable. Have many failed?

I was going to suggest aliasing, but someone beat me to it.

Intel is an interesting source for voltage regulators.

I am not responsible for the design, has been tasked to debug it. AFAIK they have seen a fair amount of the failing. Also without any load, just hooking up a debugger before programming the controller that is the load

From my point it looks like a SCR latchup, or the internal gatedriver failing due to high dv/dt. But, it must be just on a knives edge, since some parts never fail

It is certainly a nice part, high frequency, high efficiency and low outline

That part has separate digital and analog supplies. I've seen parts that latch up if those get far apart.

I hope your board doesn't have separate analog and digital grounds.

If they've popped around zero load, that's where to look.

Hit it with short transient loads from zero. Try a few line input cycles with no load. . . . and freeze spray it to ensure it's not a cold start issue.

You can monitor the input and output but it may be more important to pop one under known conditions, to know there's something to look at.

I'd advise no scope contact to the internal node until you've popped one. After all, that's one of the known preconditions - ie no contact.

RL

Probably unrelated to your question, but FYI, those things go nuts when subject to ambient noise, in particular, surge waveforms coupled electrostatically to the sense pin, as near as I can tell.

Did one EMC review on a product that would reboot when its main board (with SoM, FPGA, and PoL converters -- those things) was nearby some wiring that's exposed to the outside world (mains transients). Customer was reluctant to spin the board (lots of layers, sunk-cost-fallacy from already spinning it a handful of times..) so opted to put a hunk of metal (shield) above it instead.

As for your waveform, is that not simply aliasing from the display or acquisition? Try peak detect acquisition mode?

Nothing you can do about the transient, I presume you've already got bypass caps as close as possible, and that's the only thing you have control over. I'd love if they made regulators with a separate drain pin so I can add snubbing to it, but nah, who would ever want to do that...

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website:

They bought Empirion some time back if I have the name right. They debuted POL converters with an integral inductor using some special technique that I don't recall. The few times I had a use for them the 5.5V input max was the show stopper.

To Klaus, have you checked that this is not a manufacturing issue shorting the output with a solder bridge? A QFN can have shorts under the chip. Maybe there's something goofy with that?

The analog and digital grounds are hard connected

Other people have done full transient load test, but good point, maybe I should redo them to make sure nothing was missed

Yes, that's always the problem. Probing it may remove the fault. Not probing it, you don't know what happened

Yes, soldering is not the issue. Some fail right away, other fail after long time operation

That is a test I have planned, using some external field probes. But your input could add to that to use a small copper area and apply a square signal to it, to produce not just magnetic fields but also electric fields

Yes. I did the measurement on a fast scope, triggering on the peaks.

The recommendations from Intel has been followed. So special input caps. Only thing that caught my eye was that the output cap is not capacitive at 4MHz (operation of device), but instead passed the resonance point to be inductive, however it still has low impedance. So in principle the internal device caps are in parallel with an external inductor at 4MHz. Intel said it was ok, but I still don't like it

The agnd and dgnd pins of the chip solder to exactly the same, single ground plane?

Yes. No funny beads or anything like that ?

Just making sure. Some people like to split grounds.

Could the +5 input be spiking too high?

Nothing to stop probing of AVIN, PVIN, VOUT or PK pins. Measuring local input and output currents can be tricky.

The no load Vin vs Vout waveforms suggests that there is no reverse current flow when Vin is forced to zero. This would be difficult to achieve in any buck regulator that uses mosfet switches. So there's something going on there that is atypical.

Sync Recs and control loops can do funny things around zero load. Some circuits complicate things by going into 'power saving' modes - not always a smooth transition in either direction and possibly involving timing circuits that have their own quirks. No mention of that in the literature for this one.

If external sensors produce control discontinuities that last for multi-normal switch timing periods, the low integrated inductor values used can develop larger than optimal currents - levels not normally associated with zero load.

Anything that results in reverse output current will force the switching node above the input rail, with non-ideal switching transitions.

In the device block diagram, neither an undervoltage nor an overcurrent detection triggers a slow-start. We can't see how the fixed-frequency timing is intended to deal with asynchronouse events, or how the circuit deals with revese inductor current. Block diagrams can conceal as will as illustrate.

RL

In order to determine if there is a variation in the peak, you need to trigger on a non-peaky part. If there is real variation, your display should show alternating images of non-peaked and peaked waveforms.

If there isn't a non-peaked waveform to see, then your longer trace is aliased.

RL

Yes, I triggered on the peaks. Then zoomed out to have 10 cycles and the envelope was visible. Both high peaks and low peaks. Sample rate and number of points was sufficient to show all detail