SERIAL PERIPHERAL CONTROL REGISTER (SPCR) In most systems, this register is written only once shortly after reset to initialize the SPI system. Bit 7 SPIE reset 0 SPI interrupt enable 6 SPE 0 SPI system enable 4 MSTR 0 Master (1) or slave (0) mode select 3 CPOL 0 Clock polarity: 0 active-high, 1:active low 2 CPHA 0 Clock phase (basic protocol) 1 SPR1 0 SPI master bit rate 0 SPR0 0 " " " "
SPIE
0 = SPI interrupts are disabled
1 = SPI interrupts are enaabled if SPIF and/or MODF is set to one.
SPE
0 = SPI system is turned off.
1 = SPI system is turned on.
MSTR
0 = SPI is configured as a slave.
1 = SPI is configured as a master.
CPHA The clock phase bit, in conjunction with the CPOL bit, controls the relationship between the data on the MISO and MOSI pins and the clock produced or received at the SCK pin. CPHA selects one of two fundamntally different clocking protocols to allow the SPI system to comunicate with virtually any synchronous serial peripheral device.
SPR1/SPR0 These two serial peripheral rate bits select one of four bit rates to be used as SCK if the device is a master; they have no effect in slave mode. SPR1 SPR0 Internal Processor Frequency if XTAL Clock divided by is 4.0 MHz 0 0 2 1.0 MHz 0 1 4 500.0 KHz 1 0 16 125.0 KHz 1 1 32 62.5 KHz
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.