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SPI Configuration

Hello,

I am trying to interface an MPC5554 procesor with 68HC908 processor using SPI ( Serial Peripheral interface). MPC5554 is the Master CPU. I have little experience in configuring the SPI in low level. I would like to know the following.

  1. What are the factors that I should consider while selecting the Clock Polarity and Clock Phase? In my case both Master and Slave CPUs support Clock Phase and Clock polarity of 0 and 1.

  1. What are the factors that I should consider while deciding the delay between the slave select signal and the first clock edge also the delay between the last clock edge and the slave deselection? i.e. The delay between Slave select going low and the first clock edge.

  2. What should be the optimum time difference between the transmition of two message frames?

It will be very helpful if somebody can throw some light on this.

Thanks and Regards, Sreeram.

Reply to
Sreeram S
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I see most devices clock data in on the falling edge, although some are on the rising edge.

This is meerly a setup time for the internal gates, a safe bet is 1/2 clock cycle.

Not sure what you mean, the data rate is based on the clock, so skewing of clock and data makes no difference to the slave.

Reply to
Martin Riddle

Try reading datasheet from Microchip, they cover SPI buses quite extensively with comprehesive diagram. The SPI bus serial data need to settle HIGH or LOW before either rising or falling edge of the SCLK, depending on SPI configuration. If both device is SPI hardware, then it just matter to get configuration right and the hardware deal the rest without worrying about the timing since they SPI standard.

Where the timing is important, is the speed to transfer data into internal register and take it out quickly before collision occurs (via flag which may block further SPI data...check datasheet). This is where interrupts thread might be useful.

Good luck

Mart> In-Line...

the rising edge.

cycle.

clock and data makes no difference to the slave.

Reply to
riscy

Who would write a SPI slave or master code without using interrupts?

to

on the rising edge.

cycle.

two

clock and data makes no difference to the slave.

Reply to
Martin Riddle

Well, I for one. I just finished a design (hard- and software) where an AVR controls two DDS's and two DACs. I used no SPI interrupts on the AVR side simply because I didn't need to. (overkill)

Meindert

Reply to
Meindert Sprang

I'd go along with that (at least for master code - I haven't implemented an SPI slave). Frequently, the SPI bus runs so fast that it is far easier just to wait for each byte transfer to complete rather than implement interrupt systems. I've used micros where the interrupt overhead is longer than the transfer time, so it is significantly faster to use polling! Of course, this depends highly on the speed of the processor - I'd hardly want an MPC5554 to wait around for an SPI transfer (that's what its QSPI module is for), but it makes a lot of sense on a 68HC908 chip (although you would want to interrupt on the chip select).

Reply to
David Brown

I dont understand how the clock phase, polarity and delays between Slave select and clock edges are related to using interrupts. In my case since both master and slave are processors, all the parameters are configurable and I wanted to know the factors that are considered while deciding these values. The tranmission and reception of one full message frame ( byte ) is handled by hardware. Interrupts are only used for copying into tranmsit register and copying from receive register. Polling does not suit my requirements since both the processors are heavily loaded. If the delay between slave select and first clock edge is meerly a set up time for the gates, I feel one clock cycle of the slower device is a good figure Regarding the clock phase, both master and slave can latch data on both the edges. so ideally speaking all the phase polarity combinations should work.

Regards Sreeram.

AVR

side

Reply to
Sreeram S

They are not related - they are different (but relevant) issues.

That's entirely up to you and your application requirements. Just make sure the slave can respond to the interrupts fast enough - SPI interfaces are generally not buffered in the way UART interfaces are.

It should work fine with any settings as long as they are consistent.

Reply to
David Brown

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