Hi,
I am aware that the best way to create a seed (for random numbers) is external hardware, but does anybody know any cheap-and-easy tricks to generate a random-ish number on an FPGA.
Kristoff
creating a seed on a FPGA.
May 04, 2017
6 Replies
Read the LSB of the voltage monitoring in xilinx sysmon to get each bit of your number.
Colin
Or for sufficiently random request timing, keep a clock running and use the clock value for the seed.
Or combine the two.
I seem to remember doing a web search on this a while back -- there are a lot of papers, of varying degrees of technical soundness.
www.wescottdesign.com
Xilinx has many app notes on this - it's a common requests. Here's one I've read in the past, but there's others:
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Regards,
Mark
I thought this issue had been solved?
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Rick C
I was going to suggest asynchronous ring oscillator, but yours is downright elegant.
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.
I built a very wide version of this several months ago to do testing in the lab but it hasn't been tested yet. I'll have to report back after my cowo rkers try it out. You do have to instantiate LUT primitives to get it to s ynthesize. I don't know why the app note didn't address this nor supply an y example HDL.
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