RISC-V Support in FPGA

I thought about my historical code some more, and I realised that I did have some examples of behavioural GF multipliers that didn't work as well as the same function expressed as a bunch of wide xors.

The particular example I'm thinking of had a 128 in, 128 xor tree that really shouldn't be any harder to synth than a CRC. It's a linear mapping stage in an SP block cipher (like AES, but not AES (which has a relatively weak mixing function)).

Vivado gave (IIRC) 11 or 12 levels of logic rather than the expected 3 levels of logic. Hmmm. The revised source code (expressed as a bunch of xors) produced 4 levels of logic, and routed to speed.

BTW, I used my VHDL testbench for the original function to write out the VHDL for the xor tree.

I think that carry chains (and similar structures) became less important for wide functions once six input LUTs became commonplace.

The Xilinx DSP48E2 has a wide xor mode that I think can give a 96 input xor in a single DSP48E2 slice. I've never tried it.

Regards, Allan

Same here. I have constant multiplier matrices and each has a column weigh t of about 160 so I end up with a 160-input XOR for each column. Ideally t hat would be log6(160)=2.8 levels. First I have to use very low-level co de and even then Vivado shares subexpressions too much and I end up with 6 levels unless I isolate column groups in different modules. If I isolate e ach column in its own module I can get the 3 levels. Isolating column grou ps also means they are placed as a group which reduces wirelengths.

Yeah, I looked into this at one point but decided against it for a few reas ons. I thought a nice feature would be to be able to turn off the carries in the DSP48 and then you could use them for GF multipliers. I have used D SP48s as GF(2) accumulators and I've used them as transposers to extract co lumn data from rows stored in RAMs.