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reg: clock generatred by combinational logic

hi

i am designing one receiver which had 2 data input lines(indatax,indatay) and i have to extract clock from that. with change of data(ie.comparing present bit with previous bit ) i have to genrate clock. so i used ex-or logic.like this

if ( (x xor indatax)= '1' or (y xor indatay)= '1') then if ( var = '0') then intclk Clock Signal | Clock buffer(FF

name) | Load | > -----------------------------------+------------------------+-------+ > clk | BUFGP > | 61 | > invclk | BUFGP > | 2 | > I_intclk:O | > NONE(*)(dataword_15) | 44 | > -----------------------------------+------------------------+-------+ > (*) This 1 clock signal(s) are generated by > combinatorial logic, > and XST is not able to identify which are the primary > clock signals. > Please use the CLOCK_SIGNAL constraint to specify the > clock signal(s) generated by combinatorial logic.

so how shud i overcome..plz help me in that

thank you. vinod

Reply to
vinod
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Hi,

you should try not to use combinatorial clocks, that leads to an asynchronous design. Instead use outputs of registers.

Reply to
ALuPin

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