Read back FPGA configuration

All,

Neil is right, that the ISE tools do not support readback (only verify). But the silicon can (of course) read back its bitstream to any device that is programmed to provide the necessary commands to the device to do so (otherwise, how would verify work at all?).

For example, the Rosetta experiment uses JTAG readback to find soft errors caused by cosmic ray neutron showers.

(by the way,

Aust> Sadly, FGPA readback is not supported at all. You can, however, perform

Yes, but please include the full URL too. You never know when some nice service might vanish.

In this case, it's:

Hal,

They claim it never goes away. (Until they go out of business....)

I'll post both, but I have received back that the long ones are useless to most folks as they can't cut and paste them back together sometimes for their browser of choice.

Aust>>(by the way,

Thanks for the answer guys. Is there any other way (tool) to accomplish the readback? I've been trying using JTAG tools (a openwice project) which is nice and neat, but it does lack of documentation and is taking me too much time to program the subrutines for xilinx devices (JTAG tools doesn't support Virtex at the moment). Austin,I read the article, very nice. Actually I need this readback stuff because I'm trying to implement something similar, kind of an artificial SEU generator, a SEU simulator if you wish. Any suggestion would be great! Alonzo.

it maybe tedious but it is always possible to cut&paste into a text editor to fix it up and then paste the whole thing to the browser. i can't believe there are browser which prevent a whole url to be pasted to the link box.

mk,

It may be possible, but not all folks have the skill.....(believe it or not).

Aust> >