> >
> > > Or maybe there is a way to configure NIOSes SDRAM controller to support
> > > two NIOS CPUs instead of using that external arbiter?
> > >
> >
> > The second thing I can suggest, and would recommend, is to make use of
> > our own bus arbitration logic. You can in fact connect two (or more)
> > masters (two Nios', DMA, your own custom master, another
> > microprocessor) to any avalon slave, including the SDRAM controller.
> >
>
> I believe that in the end I will use this controller, but for now I just have
> to use the "external" arbiter, because this controller/arbiter allows me to
> access the SDRAM directly through the PCI (the development board is a PCI card)
I've decided to use Nios'es SDRAM controller, so please disregard my last question - that third-party arbiter caused too much problems.
So thanks anyway, Yevgeny