Hal,
Filters with a Q of ~ 100 provide a fairly substantial reduction of jitter (~20:1 measured reduction in jitter with Q ~ 120).
LC at least. Crystal not required. RC too low Q.
Aust> >So clever people used the DDS to create a sine wave, then filtered the
>sine wave with an analog filter, then used a comparator to slice it back
> >into the digital domain, with reduced jitter.
>
> What sort of analog filter do I need for this approach?
>
> Do I need a serious narrow band pass filter? Aka a crystal if
> I want a real good one, which probably means I should just get
> a packaged osc.
>
> Or will a simple R/C low pass filter that cuts off at the target
> frequency provide enough attenuation at the 3rd/5th harmonics
> to make a low-jitter clock?
>
> R/C filters are pretty cheap. You might need some ugly op-amps
> and more Rs and Cs to get several poles. [But logic is cheap too,
> especially if you already have an FPGA and board space is critical.]
>
> > But it is a tortuous detour, and faster multi-phase DDS
> > seems to be so much simpler...
>
> That just reduced the jitter by a factor of "multi". Right?
>
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