ProAsic3 (PA3)

This week the Actel FAEs came in to tell us about a problem with the pro-ASIC plus chip. It seems the flash retention rate is much lower than expected when using designer prior to 6.1 due to a load balancing issue across transistors. Unfortunately, they don't have a write-up of this problem on their website yet.

I am meeting with a sales rep and FAE on these products tomorrow, opps, today. My main concern is that they are not slated to be out until Q4 although I was told possibly Q3 (meaning end of Sept). I also want to hear some real pricing instead of the "as low as xxx in quantity".

I was told that the larger parts would be out first. So if you want a $1.50 part you will need to wait until '06, I expect.

The data sheet talks about being 5 volt tolerant, but they aren't. They just do the same game of using resistors like the Virtex, etc. parts.

I don't see the pulldown on the TRST as being much of a bug myself. My experience has been that every part handles the JTAG signals in different, often incompatible ways. But if you use the spec'd pull ups or downs and use their cable the JTAG should work just like TI DSPs and Xilinx FPGAs.

I'll let you know what I find out from the FAE.

the

Please do so!

The first part out is 600E that was known already at Electronica 2004 (that is nov 2004) hm are you saying no parts will be available til Q4 ? that would be pitty!

Most vendors dont admit silicon bugs! You need to prove their silicon is faulty then in some case with long delay they might agree yes there is a problem.

Antti

I'm not sure, but I think, the fact that Actel has mostly highpriced devices means that the applications were the fpgas are used, are also high valued. This means that systematically failure tend to be more expensive for Actel.

I use some for prototyping and I am very satisfied with. The only wish I had are 5V IO Buffer. Unfortunately there seems to be no reprogrammable device with 5V IO and sufficient cells on market to do prototyping for Asics with 5V IO.

bye Thomas

PA3

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Xilinx

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I seem to remember that the JTAG spec requires(recommends) that TRST is optional. That is it is not require to perform any of the JTAG operations, including powering up. As far as a bug. We had 2 unexplained catastrophic field failures (parts actually were fried) of the Plus device before I was able to figure out the problem in the lab.

Some of the parts that fail to power up correct started to go into thermally run away. Eventually they would overhead and destroy themselves. It is one think if it powers up brain dead but another when it destroy itself and half of the other components on the board.

My main issue is the fact that they do not notify customer of problems with the device. I always felt like I was the only one having problems with the device, but I am not so sure now.

I don't believe that is correct. The TRST pin is optional, but it does not have to allow the part to work if not driven to the correct state, as in the JTAG cable can ignore it.

I have not looked at the programming process, but isn't there a signal to indicate a programming failure? The SRAM based parts have that.

Here is what I found. The 600 is the first part out of the chute. It will sample by April, as in *we* can get samples then. We never got to a production date because the part does not fit my socket. The lack of

5 volt tolerance and the schedule keeps it off my board. I also did not really get much on pricing.

A thing that I found very surprising, I was told it is not really field programmable, as in by a MCU. It has to be programmed by cable because you have to supply +16 and -13.5 volts (or similar). So if the chip can take these voltages, why can't it handle 5 volts on the IOs??? Obviously they are switching high voltages without problems.

are you sure its 600 not 600E ?

600E is supported by free tools, 600 not :)

the samples did exist in october 2004! just not for regular mortals :(

NO NO! the +16.5 -11.5 are for ProAsic+ not for PA3 ! PA3 works down to 1.5 single supply and needs 3.3 for programming

Antti

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To be more precise, the default state of the pin (left unconnected) will allow the JTAG to work properly. That is you do not have connect anything to the pin in order for the JTAG to work. It is in the spec.

lab.

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ProAsic parts are Flash parts you only program them once, they are non-volatile, there is no "programming" on power up like the Xilinx or Altera. The device is ready to go immediately on power up.

Maybe I did not explain this well, The issue is that on power up the JTAG circuits powered up in a undetermined state which cause the boundry scan circuit to do bad things to the IOs. Causing the device to not work because it had no control over the IOs. I believe what happen on some of the parts was that the boundry scan cause contention inside the device which cause the thermal run away.

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Which free tools? :-)

-Toby.

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 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

actels tools (free versions) support the smallest of each family

600E is smalles of PA3E :) for the non-E only the very small are supported by the free stuff well actually nothing is supported as the current Libero/Designer that has PA3 support as advertized doesnt actually generate programming files for any of the PA3 at all, so nothing is supported that both for free tools users as for paid licensees

Antti

The problem you reported on the I/O register clear polarity is a real problem in the Designer software (Thank you for pointing it out) and will be fixed in the next service pack of the software.