placing addiional caps across existing caps to reduce noise

I don't know how you measured this. The measurement data I have seen clearly shows this resonance. But it was not my data, it was from someone much more knowledgeable than myself.

I don't doubt that there are many ways to skin a cat. But I have seen for myself boards that did not work well because of power decoupling problems. The biggest symptom from poor power distribution is general flakeyness. Often this is misdiagnosed as an SI issue, which I guess is not totally wrong. But now I realize that the proper cause of poor edge rates and some portion of bounce problems is in the power distribution.

With no caps I would expect you have to be designing board with very limited IO and low current devices. I seriously doubt that his method would work on every product. The real point that was made in the class I took was that you need to evaluate your power decoupling needs rather than just applying a "rule of thumb". I guess some people do their evaluation by saying, "I don't need no stinkin' caps". ;^)

The complementary measurement is to use the same SMA tap to measure plane noise on the operating board, which is a good way to verify theory. I do boards that mix FPGA's, Eclips, uPs, fiber optics, PLLs, VME interfaces, and precision delay generators, and they all work at picosecond jitter levels. So far, close planes and reasonably scattered 0.1 or 0.33 uF 0603 bypasses have always worked.

John

the

mini-plane

Hi Martin, Right. That's my reasoning. Cheers, Syms.