placing addiional caps across existing caps to reduce noise

If the tool says the SRF is 3 GHz, I can't argue with that. But I don't believe it. The SRF for a 1 uF 0402 cap is typically below 10 MHz. Even many "low inductance" capacitors have a SRF of below 200 MHz. This is a very big discrepancy and will change your entire perspective if it is wrong. I susgest you verify this number. Is it possible that the SRF is 3 MHz?

With a SRF below 10 MHz, it does not matter a lot where the parallel resonance is. There will be a wide range of frequencies between the SRF and where the plane has a low impedance that will have a very high impedance irrrespective of any resonance.

Another thing, "high" ESR is good, but not so high that it interferes with the function of the capacitor. With a 1 ohm ESR it will not be a very good capacitor at lower frequencies where it is supposed to be capacitive.

Reply to
rickman
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Yes, he added an LDO between the switcher and the digital power because the digital power goes to the GPS module. This is a bit pointless because an LDO is only effective up to a few 10s of kHz. Then there is a ferrite bead which is not very effective until you get to high MHz. So that leaves a huge hole from about 100 kHz to maybe 100 MHz. Also the ferrite bead is only an impedance, not a cure. Noise can still couple to the load if it is not a low impedance.

On the other hand a good power plane will decouple noise at the source and prevent it from reaching the ferrite filter. So good power planes are *always* a good thing for reducing noise.

How do you make a capacitor less effective at low frequencies??? Wouldn't that be an inductor?

I don't know about the royal lineage. I do know that digital circuits are kept quiet with good power decoupling including low impedance across the spectrum. In this case the only way to filter 1.5 GHz in the power spectrum is with plane to plane capacitance.

Reply to
rickman

I think you should talk to the RF guy about that. He is responding to problems he had in the past that were fixed without understanding the cause. So now he is using the same bandaid to a problem that does not exist. BTW, the LDO he used in another design was to fix a noise problem in an audio circuit that obviously was due to lack of good power supply design.

I see the main path for noise being the power distribution. If you keep that clean the only other path is coupling by emitted signals which are also reduced by good power decoupling.

I had a conversation with him where I learned that his LDO in the digital power was a response to touching a hot stove. I don't have a lot of respect for that type of engineering. I also don't respect engineering that does not address problems with understanding. Rather than learn why the switching supply was making a low frequency noise he now adds LDOs to the power path for all digital circuits. That would not be so bad, but this is battery operated equipment and this has increased our power budget by over 13%.

Anytime someone can show me a problem and tell me how an approach will solve the problem I am happy to listen. But adding circuits when there is no problem is not a good idea.

I don't consider that to be the discriminator of what approach is correct. The digital circuitry is very small and likely not to create any major problems. But it is also likely to cause a small decrease in sensitivity that might be hard to measure without doing a performance test. I know they will not be doing any performance testing on this receiver. They will just fire it up and see if it can find the satellites in the factory. So no one will be right and no one will be wrong.... until the customer compares our units to a comercial GPS receiver and we don't hold track as well. But then it will be far too late to make changes. It would be much better to do it right the first time.

Reply to
rickman

previous

I think you've missed the point I'm trying to make. I'm trying to point out that small planes do not have a bypass resonance problem.

1) With a tiny plane, the resonance between it and the bypass caps is at a very high frequency. 2) At this frequency, the bypass caps have a high ESR. 3) This damps the resonance so much that you don't have a any problem at all.

At no point did I say that a 1uF cap had a SRF of 3GHz. (BTW, you're quite correct that it's at about 10MHz) I did mention its ESR at 3GHz to give an example of how the ESR increases with frequency. The frequency we are talking about is the resonant frequency between the plane and the bypass caps.

HTH, Syms.

Reply to
Symon

All capacitors are less effective at lower frequencies. They don't do much to your kHz signals whereas an inductor can be a dead short at the lower frequencies. It's just that if you use a 10 pf RF capacitor with appropriate multi-GHz leads for stripline design, you won't do a whole lot at 100 MHz but where the circuit is used - the GHz realm - this low-value capacitor can provide excellent RF bypass.

Digital circuits are clocked, extremely wideband devices. RF is typically narrowband. Also, the power supplies are typically filtered in stages on the receive side such that the highest level output (IF amplifier out, perhaps) is closest to the "main" rails while the next stage down is filtered from that filtered rail. This goes down until you're at the Low Nois Amplifier attaches to the antenna where the power has passed through several filter stages. If everything was connected to one power/ground sandwich, the circuit would be losing its lunch. No sensitivity at all.

About the only way to filter 1.5 GHz for a digital circuit - extremely wideband by nature - is with distributed plane capacitance.

I still suggest that RF is a different beast where power planes are no help.

Reply to
John_H

This discussion has gotten so interesting, I think try it is the only thing left.

I'd front the few hundred dollars, and some layout time, to take 2-3 designs and lay them out with the Xilinx guidelines, Rick's guidelines, and Symon's Guidelines and do a bake off if somebody would provide the parts. Say 3 pieces of a 6 layer 0.063 FR4 panel that is 16" x 22", would allow for 2 projects that are 7" x 8", or 3 projects that are 5" X 7".

Should be fun :)

Reply to
fpga_toys

You mentioned an ESR at 3 GHz. ESR is important near SRF and at resonance points, not much use elsewhere.

as for your points

1) your cap/board resonance problems are just moved with smaller planes, not removed. Another problem is resonance either between caps with SRFs far enough apart (given the associated Qs) or caps that are inductively far apart, forcing the different SRFs to the perspective of a specific noise source.

2) an ESR of 1 ohm isn't so bad if you have a dozen caps "nearby" but 83 mOhms still isn't that great for high power problems

3) Ah, life with no problems. Resonance between the cap and plane might not be such a problem if the Q drops as the frequency increases, but what impedance solution are you achieving? If you need more high-SRF caps to bring down the impedance beyond the SRF, the effective ESR of the "solution" is lower and resonance is still a consideration. Isn't it?

I'd suggest that most of the folks in this forum don't need the 3GHz performance because the packaged digital logic is loally bypassed in the package and the silicon so they don't "feel" much above many 10s of MHz, at least according to the recent Howard Johnson talk. It's the other discretes on board - the unpackaged or "low package" devices that feel the brunt of the plane problems.

...and EMI.

Reply to
John_H

Agreed, but ESR is a bad thing at the SRF. It's a good thing at parallel resonance, e.g. between bypass caps and plane. That's what I'm addressing here.

not

Agreed, so if this parallel resonance moves to a point where one of the resonant parts, in this case the bypass cap, has a large ESR, the resonance can't happen as it's damped away.

I'm not suggesting that decoupling at 3GHz is useful. In my opinion, any decoupling at frequencies above a few hundred MHz is useless because of the package impedance at these frequencies.

not

"solution"

To repeat myself, I don't care what the impedance is above a few hundred MHz. This 'threadlet' starting with Martin's post is addressing mini-plane resonance issues, not bypassing. I wish I'd never mentioned 3 bloody GHz now! :-)

at

discretes

Agreed! Cheers, Syms.

Reply to
Symon

Which is a real design issues as we have FPGA's which have the ability to clock internally above a few hundred MHz, and the VCCINT pins have strong frequency components spaced at multiples of the LUT propagation delay, and the short inter-CLB interconnects. And, with each generation, they move higher up the scale.

All the issues are related, particularly since Austin started this thread in response to my posting that I stacked caps as a secondary check that there was enough bulk capacitance in proto layout, in a case where I thought that the chip/package was unable to handle worst case designs.

Reply to
fpga_toys

I misunderstood. It is getting a bit pointless to continue to discuss this as the only thing that is important is how it works. We can get info on how we expect it to work by doing simulations and analysis, but measurement is the only way to be sure. But I don't think we even agree on what constitutes the requirement in terms of impedance.

A tiny plane will have nearly no capacitance. The resulting resonance is not important since the plane will not be doing much good as a capacitor.

I don't understand what problem is being solved by using a small power plane. A large power plane is useful when used with a combination of values of caps with low Q values. This arrangement can work well with three values of ceramic caps and one value of tantalum cap and give a relatively flat, low impedance from 1 kHz to well above a GHz. But if you cut up your power plane so that it is very small, the upper end will be limited to a few hundered MHz which is not fast enough for many applications with fast edge rates.

Using a single value of ceramic cap will never provide a low impedance above 100-200 MHz and without a sizable plane will result in a high impedance that will cause edge rates to slow and potentially induce excessive bounce lowering your noise margin. With a full power plane closely coupled to the ground plane you are likely to have a resonance causing a high peak in the impedance around 100-200 MHz. Sure you can use 4 or 5 times the number of caps to lower this peak, but why do that when you can do it more easily with fewer caps?

Reply to
rickman

I am not aware of the HJ talk on packages limiting the need for high frequency decoupling. But I seriously doubt that this is an accurate statement if it was made. If a chip can produce a rise time of 0.5 nS then clearly the power plane is providing enough current at very high frequencies to drive the transmission line. I don't see how the chip could possibly provide enough coulombs to drive the line without the power coming from the power plane.

Is it possible that HJ was referring to the packages with higher lead inductance (any type of leaded package such as SSOP, TSSOP or QFP) compared to BGA and CSP?

Reply to
rickman

This is a GPS module. The you are talking about the power normally delivered to the analog portion of a receiver design. This filtering was put on the digital section of the GPS module. The LDO accomplished

*nothing* since there was no reason to suspect noise in the bandwidth the LDO could filter. Since the digital section would make its own noise, I see no point to adding an inductor to the path from the switcher to the digital LDO. The only inductor he put in the path to the RF was the ferrite which was only effective in the hunderds of MHz. There are lots of frequencies in the noise that can easily get into the RF section and mess things up. Noise does not have to be on the carrier frequency.

This is a poor design and leaving off a power plane just compounds the problem.

Isn't 1.5 GHz RF? If the noise is present on the power rail at this frequency it will be radiated by every part that is connected. This will be picked up by any other circuitry in the area and possibly even the antenna.

So instead of providing power planes to prevent the high freq current from creating EMI, they are adding cans around the various circuits. The GPS module already has a can on it. Our digital design has not one, but three to isolate each section of the circuit!!!

I am totally convinced that this guy is winging it and has no concept of how to deal with EMI. Basically he has been working at this place for the last 10 years (where cost is often not an issue) and has not learned much about how to best deal with EMI. Instead he has learned a handful of "tricks" that work as long as you don't care about how much your solution costs and you don't mind tweeking the design after it is built.

Reply to
rickman

Rick, I totally agree. Both your designs and mine work, and we've had a robust but civil and highly enjoyable discussion of the issues. I've certainly learned some things from this conversation, thanks for your time and thoughts! I still disagree with the other points in your post, but I've already detailed why in my previous posts, so I'll just have to live with that. Thanks again, and best regards, Syms.

Reply to
Symon

It was a BGA package with on-package decoupling and - for highest frequencies - capacitance in the silicon.

If you ask yourself how many coulombs are associated with a single switching event and compare it to the energy stored in an 0402 capacitor you might be surprised. These things look nearly like AC shorts at their SRFs, after all.

Reply to
John_H

I sometimes add a few SMA connector footprints to multilayer boards so I can TDR the planes. As near as I can measure with my Tek 20 GHz TDR, on a bare VME-sized (6U) board, good parallel planes look like an ideal capacitor, with no evidence of edge reflections or anything like that. And as you load ceramic bypass caps *anywhere* on the board, the value of the ideal cap increases. So it doesn't much matter where you put bypass caps.

The planes are a better cap than any discrete parts. Keep the powerplane to ground dielectric thin, 5 mils or less, to keep the plane capacitance high.

John

Reply to
John Larkin

There's nothing wrong with a cap being inductive as long as the inductance is low. If somebody made a 10 farad 0603 cap, its SRF might be a kilohertz or something, but having more C, and operating above srf, doesn't make it any worse a high-frequency bypass. I figure the more C, the better for any given size.

PCB planes are a big, lossy, many-nF capacitors (or, if you prefer, big, lossy, super-low Z transmission lines), and adding lots of, say,

0.33 uF 0603 caps just makes it better. All this stuff about Spicing staggered srf nulls is silly, given that the caps aren't out in space, they're soldered to the huge low-z lossy power planes.

John

Reply to
John Larkin

Have you verified that you can use a 50 ohm TDR to effectively measure impedance around 1 ohm and less?

Measurements have been made by others that suggest your readings aren't telling you the whole story. It's possible the others are wrong and you're correct but it seems there are several sources suggesting that a

6U board will NOT look like an ideal capacitor without inductive or transmission line effects.
Reply to
John_H

and

As I understand it, the reason you don't care above a few hundred MHz is because you are doing mini-planes? If you were doing whole board planes, then there may be problems above the "package frequency" due to the PCB radiating at a frequency which is not "well-decoupled" even at several hundred MHz. With a bigger plane, this is more likely.

Or have I misunderstood?

Cheers, Martin

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
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Reply to
Martin Thompson

Another country heard from!

John, no one is saying more C is not better than less C. The question is how do you provide *enough* C to do the job in the most cost effective manner and be sure you have done the job right?

My point about the caps being inductive is that where a cap is near its SRF, the impedance is much lower than either the capacitive curve or the inductive curve. If you draw the impedance line for the equivalent inductance and for the pure capacitance, they approximate the true impedance of the part anywhere that is not near the SRF. So when I talk about the region where the cap is inductive, I am talking about the impedance rising to a point that it is no longer low impedance.

Well, I didn't know that "silly" was a technical evaluation. I guess if you are designing a board for Jerry Lewis you should calculate the SF (Silly Factor) as part of your evaluation. I think you are proving my point. The caps are on a plane that will resonate with the caps. So you can't just say adding caps will lower the impedance across the bandwidth.

In fact, however, adding a single value of capacitor to a power plane is likely to produce a parallel resonance (with a higher impedance than the plane by itself) at a frequency that you care about. This can be mitigated by the ESR of the caps which will damp the parallel resonance. The data I saw showed that using 0603 caps of 0.1 uF will produce a pretty healthy impedance peak in the 50-100 MHz range, of course depending on the details of your board. This is a bad place to have an impedance rise when you are looking for the caps to lower the impedance.

A lot of people here seem to think that you can analyze this on paper or with words. I have seen the simulation results and the measurement results of real boards, so I am inclinded to believe that over any paper analysis which may or may not be correct for a real board.

Sure, you might be able to make your board work with a hundred 0603 parts. But wouldn't it save money by reducing the routing congestion on your board if you could reduce that to maybe 20 parts of three different values? It certainly would save time in layout and may even save you a pair of layers in a close board.

Reply to
rickman

Except that, when you measure it, they do.

A scattering of 0.1 or 0.33 uf ceramic caps here and there about a power plane will not induce meaningful resonances, as far as I can measure. The only mistake I have ever made on multilayer boards was using too many bypass caps. Lately I use four 0.33 uf caps per supply per FPGA, and even that's probably overkill.

I have seen a number of simulations that were absurd, generally - surprise! - performed by guys who sell caps. What I believe are TDR measurents on unpowered boards and plane noise measurements on operating products.

All of my boards work as described. The reason there are so many opinions about bypassing is that most everybody's approach works. I know one guy who doesn't use bypass caps at all, and his boards work too.

John

Reply to
John Larkin

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