I would love to see some data to support that statement about the lower inductance. I don't have Ritchey's book handy, but I seem to recall that moving the vias from the end of the pads to the side was only a small delta in total inductance (significantly smaller loop area). I expect that moving them to the center would be another small delta. This has to be considered in the context of both the inductance of the device itself as well as the result on the impedance of the board.
I think you will find that small changes in inductance do not have a major effect on the utility of the caps. If you use multiple caps with mutiple values you can get a low impedance over a wide bandwidth with a minimum number of caps. I have no doubt that using via in pad will help to raise the resonant frequencies, but I think you will find that if you do all the other things right it will not make much difference in the end.
Won't any higher inductance result in the same above-SRF slope? That is, given the total inductance, it won't matter what the capacitance is once above an ohm in the impedance vs freq plot.
I've seen good information on Cadence tools based on Sun Microsystems work that tracks what you've described with Ritchey. A recent Howard Johnson / Xilinx talk also covered many of these items well without contradiction.
In each case, the lowest inductance achievable was always the goal. The small deltas may be small in nanoHenrys but are probably a significant percentage.
Same-side vias are better for a cap than end vias. Vias in pad are better. Partial vias in pad are best. That's the understanding I got.
A distribution of capacitance can give a superb, flat impedance over a wide frequency range. Resonance is a problem for low ESR caps too far apart in frequency such that they cancel each other out with an LC resonance between the SRFs of the two values. Vias in pads provide better performance.
I'm not sure what you are asking. A different capacitance will not change the inductive part of the impedance curve and a different inductance will not change the capacitive part of the curve. What changes in both cases is the SRF. So you put a few 0.1 uF caps on the board and a number more of 0.01 uF caps and even more of the 0.001 uF caps. Each capacitance value needs to have sufficient quantity to bring the impedance near the SRF low enough to be effective. Then the capacitive effect of the smaller caps keep the overall impedance low in spite of the larger caps being inductive. Finally the impedance of the ground planes keep the impedance low for the highest frequency. Doing a simulation is always a good thing to be able to see how the parallel resonances affect the impedance.
The contradiction part I don't agree with. Many still argue that the distance between the IC and the cap is critical and some still say quantity is more important than variety of SRF. In one of these threads there was a link to a post by HJ. There were some things in the HJ post that were not supported by any sort of measurement or even simulation. I don't recall the details.
Not inductance, impedance. I don't care about inductance if I can keep the impedance low over the frequency range that matters to my design. The small deltas in inductance only move the SRF, they don't have a large impact on the impedance after you mix the capacitor values.
Yes, but none are really bad and it is a cost (or design/fab effort) vs. benifit. Same-side vias are pretty much free in all respects. Via in pad has some design effort if you have not done it before and some PCB vendors don't like to make them (but that varies). Partial vias (I assume you mean blind) are very expensive and clearly not worth the effort unless you are doing some really high freq work. Even then, I don't think they are needed for making the power delivery work well. Blind vias might be warranted in the signal path when you get near 10 GHz or so, but this is what I am remembering from the class, not anything I have seen myself.
Ritchey was pretty impressive because he always uses the simplest methods and verifies that it will work before he builds the actual board. I don't beleive he said he has ever used vias in pads even with near 5 GHz boards.
How much better? If your design is so critical that you need to put the vias in the cap pads, then likely you need to do a careful simulation of the power distribution to see exactly what you have rather than to rely on general guidelines that may or may not allow a given design to work.
I'm not sure what you are asking. A different capacitance will not change the inductive part of the impedance curve and a different inductance will not change the capacitive part of the curve. What changes in both cases is the SRF. So you put a few 0.1 uF caps on the board and a number more of 0.01 uF caps and even more of the 0.001 uF caps. Each capacitance value needs to have sufficient quantity to bring the impedance near the SRF low enough to be effective. Then the capacitive effect of the smaller caps keep the overall impedance low in spite of the larger caps being inductive. Finally the impedance of the ground planes keep the impedance low for the highest frequency. Doing a simulation is always a good thing to be able to see how the parallel resonances affect the impedance.
The contradiction part I don't agree with. Many still argue that the distance between the IC and the cap is critical and some still say quantity is more important than variety of SRF. In one of these threads there was a link to a post by HJ. There were some things in the HJ post that were not supported by any sort of measurement or even simulation. I don't recall the details.
Not inductance, impedance. I don't care about inductance if I can keep the impedance low over the frequency range that matters to my design. The small deltas in inductance only move the SRF, they don't have a large impact on the impedance after you mix the capacitor values.
Yes, but none are really bad and it is a cost (or design/fab effort) vs. benifit. Same-side vias are pretty much free in all respects. Via in pad has some design effort if you have not done it before and some PCB vendors don't like to make them (but that varies). Partial vias (I assume you mean blind) are very expensive and clearly not worth the effort unless you are doing some really high freq work. Even then, I don't think they are needed for making the power delivery work well. Blind vias might be warranted in the signal path when you get near 10 GHz or so, but this is what I am remembering from the class, not anything I have seen myself.
Ritchey was pretty impressive because he always uses the simplest methods and verifies that it will work before he builds the actual board. I don't beleive he said he has ever used vias in pads even with near 5 GHz boards.
How much better? If your design is so critical that you need to put the vias in the cap pads, then likely you need to do a careful simulation of the power distribution to see exactly what you have rather than to rely on general guidelines that may or may not allow a given design to work.
The discussion was on inductance with vias. If you have 1nH of series impedance, at 1 GHz it doesn't matter what your capacitance is, you'll have a degraded impedance based primarily on th L. If you have 1/4 nH series inductance, you have a 4x improvement in this high-frequency impedance. L matters for more than just SRF.
Neither the tool nor the talk suggested location is critical. I agree with you that the distance isn't terribly critical. If you have good planes - even the swiss cheese under an FPGA - your sub-nH plane inductance to the more distant cap has an adequate connection. The rule of thumb I understood was to keep the cap within ~1/10 wavelength of the frequencies of interest. The placement for a 300 MHz SRF cap is more critical than a 30 MHz SRF bulk device. I agree with you completely on this. "As close to the pin as possible" is pretty silly; unless you don't have good planes, then go for it.
The small deltas in inductance directly affect the impedance above the SRF when the L is dominant on the impedance. The frequency of interest may be above the SRF but the cap still makes a darn good bypass, retaiing the low (though increasing) impedance as the frequency increases above the Series Resonant Frequency.
For the really high frequencies, the form factor of the board plays a huge part with open-end transmission line effects felt as the power planes end at the board edge. The higher inductance lowers your SRFs and increases the impedance above your SRF-tuned "floor" possibly still within your frequencies of interest. All the improved inductance delivers in the end is a better impedance for when you can't provide any better SRFs.
I'll probably look into getting his book - it sounds like good, hard science and engineering. The rare stuff.
I would recommend good power distribution simulation. The tools haven't been so useful and available to the engineers now used to doing IBIS and spice simulations for signal integrity. The tools that are available aren't cheap, either. Proper modeling of the current sources are also a bit of a trick that wouldn't come easy to the average designer. ____
I would guess the biggest need for the extreme measures is bridging between the discrete capacitors and the disctributed capacitance of the board planes. At 10 Ghz, one might be relying entirely on the distributed capacitance. It's the ~1GHz range that might be the hardest to deal with. Simulations can show how much of a "hole" there is between caps and distributed capacitance. This hole can be addressed with unusual capacitors, vias in pad, or simply not addressed at all. Even with solid engineering, there's still a bit of an art.
I appreciate the refresh and reevaluation of my own stance on capacitors. Last time I came out about the distributed values, there were a large number of naysayers in this group. The more real-world literature we have out there - such as Ritchey's book - and the more engineers that realize the interplay, the better we'll all be able to design. For us in comp.arch.fpga, much of our success comes from the silicon vendors providing good power distribution on both the silicon *and* the packaging since our BGAs start to lose sight of the board impedance above many of the frequencies we're worrying about. Discretes on our boards are still affected by our power decoupling approach but the FPGAs start off into a world of their own within their packages.
Filled vias have an additional cost/risk, and BGAs are already a yield hot spot.
What I have seen, is what I'd call tangent vias : these overlap the pads, so that the hole is just under the solder mask. There is no trace.
Some CAD tools can also enable/disable Via sharing. Sharing is good for packing more tracks in, but poor for lowest impedance. ( fewer parallel paths result )
In extreme cases, more than one via could be beneficial, but that would impact routing channels.
If we have two caps of different values, but the same package/inductance, there's a frequency between the SRF of the caps that has a parallel resonance which leads to a peak in the impedance. For example, C1, a 1uF
0402 has a SRF of 10MHz. C2, a 0.1uF 0402 has a SRF of 25MHz. Between 10 MHz and 25MHz, C1 looks inductive and C2 capacitive. This means there's a peak in the impedance. So, the stragegy of using different values to 'even out' the impedance gives us peaks (bad) and troughs (good) in the impedance across the frequency spectrum.
However, for a 0.1uF 0402 cap, at resonance the ESR is 0.014R, so the Q of the tuned circuit is about 5. For a 0402 1uF cap, the ESR at resonance is
0.01R, giving a Q of 2. These values of Q are so low as to make the self resonance problem/advantage make bugger all difference. Note that a 10nF
0402 cap has a Q of about 3 at its SRF of 70MHz.
BTW, I got the cap data from here
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(Also, note that the vias/traces to connect these caps probably double the inductance, reducing the SRF by 30%)
As for the 'plane capacitance', it starts to have an effect at frequencies >
1GHz which is a fat lot of good when our vias and BGA balls have inductances in the nH region. Remember, we're not trying to bypass the power plane, we're trying to bypass the IC.
In conclusion, mixing different values of ceramic caps in the same packages might help a little but might hurt a little in a real system with FPGAs. I maintain that using the biggest value in the size you choose is the best, if nothing else because they have the crappest Q and this avoids BOM bloat. If we do use a range, bully for us, we probably won't notice any difference, but we have more chances for resonance and EMI failures.
Finally, I agree that the positioning of the cap is of lesser importance. However, some of us prefer not to waste layers in our stacks on power planes, we prefer to have decent grounds and route our FPGA power on layers used for signals in other places. The HF plane capacitance is pissed away by the chip mounting interconnect anyway, and its high Q might lead to evil resonances. (As you mention in your posts, Rick.) In this case, with little mini-planes for power routing, capacitor placement is crucial. (Note. With FPGAs needing at least 3 supplies, and maybe a lot more, the PCBs are getting very expensive with planes for every supply.)
In conclusion, for FPGA PCBs, Lots of ground layers, one for every two signal layers. One value of cap per size. Use lots of caps. It means less impedance. Power planes only need extend as far as the bypass caps. So, closer the caps to the target device, the less plane needed.
IMHO, YMMV, HTH, Syms.
p.s. It's easy to simulate this stuff, try the excellent and free LTSpice from
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(as recommended by Bob, thanks!) p.p.s. Let me underline, _other_ways_work_too_ , but I'm happy with this methodology, and I don't think other solutions work noticeable better.
OK, here's a LTSpice file that shows a resonance between disimilar cap values. The circuit sweeps from 5MHz to 45MHz back and forth. The first three sweeps are done with two 1uF caps, the second three with a 1uF and a
0.1uF cap. Notice the big resonance at about 10MHz for the second set of sweeps. The performance of the second circuit is slightly better at 45MHz, worse at 5MHz, MUCH worse at 10MHz. HTH, Syms.
Version 4 SHEET 1 1516 904 WIRE 1040 432 800 432 WIRE 0 464 -208 464 WIRE 208 496 144 496 WIRE 384 496 288 496 WIRE 448 496 384 496 WIRE 656 496 448 496 WIRE 896 496 656 496 WIRE -208 512 -208 464 WIRE 656 512 656 496 WIRE 896 512 896 496 WIRE 736 528 704 528 WIRE 1040 528 1040 432 WIRE 1040 528 944 528 WIRE 448 560 448 496 WIRE 800 576 800 432 WIRE 800 576 704 576 WIRE 976 576 944 576 WIRE 0 592 0 560 WIRE -208 624 -208 592 WIRE 656 624 656 592 WIRE 896 624 896 592 WIRE 1040 624 1040 528 WIRE 656 720 656 688 WIRE 736 720 736 528 WIRE 736 720 656 720 WIRE 896 720 896 688 WIRE 976 720 976 576 WIRE 976 720 896 720 WIRE 448 736 448 624 WIRE 656 736 656 720 WIRE 896 736 896 720 WIRE 1040 736 1040 704 FLAG 0 592 0 FLAG -208 624 0 FLAG 384 496 Vcap FLAG 448 736 0 FLAG 656 736 0 FLAG 896 736 0 FLAG 1040 736 0 SYMBOL SpecialFunctions\\modulate 0 464 R0 WINDOW 3 0 0 Invisible 0 SYMATTR InstName A1 SYMATTR Value MARK=45000000 SPACE= 5000000 SYMBOL voltage -208 496 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 100ns 1us 1us 1us 4us) SYMBOL res 304 480 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R2 SYMATTR Value 0.1 SYMBOL cap 432 560 R0 SYMATTR InstName C5 SYMATTR Value 1µ SYMATTR SpiceLine V=10 Irms=10.541 Rser=0.01 MTBF=0 Lser=0.4nH ppPkg=1 SYMBOL sw 656 608 R180 SYMATTR InstName S1 SYMATTR Value MYSW SYMBOL cap 640 624 R0 SYMATTR InstName C1 SYMATTR Value 0.1µ SYMATTR SpiceLine V=10 Irms=10.541 Rser=0.014 MTBF=0 Lser=0.45nH ppPkg=1 SYMBOL cap 880 624 R0 SYMATTR InstName C3 SYMATTR Value 1µ SYMATTR SpiceLine V=10 Irms=10.541 Rser=0.01 MTBF=0 Lser=0.4nH ppPkg=1 SYMBOL sw 896 608 R180 SYMATTR InstName S2 SYMATTR Value MYSW SYMBOL voltage 1040 608 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value PULSE(1 -1 12us 1ns 1ns 12us 24us) TEXT 144 344 Left 0 !.tran 24us TEXT 296 888 Left 0 !.model MYSW SW(Ron=0.0001 Roff=10Meg Vt=.5 Vh=-.4)
Having a peak is not bad if it is still below the max impedance you are trying to achieve.
Yes, this is why you need to use lossy caps and not low ESR caps. This is very important. But if you use just one value of cap such as 0.1 uF, you will likely see a much higher peak than you can tolerate. The peak will be reduced by using more of them, or you can use a second or third value of capacitance to end up with a series of closely spaced peaks and troughs that are much lower than you will get with a single value of cap. You can also use a lot fewer parts.
You should have data to back this up, not speculation and BTW, what traces? If you are connecting the caps with traces you have already lost the battle. The experimental data shows the added inductance of the via is not a significant factor in the overall picture when you use multiple values to even out the inpedance over frequency.
Again you should have data on hand before you speculate. In the Ritchey book data is provided to show that the impedance of a closely spaced power/ground plane pair is lower than the typical capacitors around 100 MHz. Of course this depends on the size and construction of the board. But clearly the region of importance is much lower than 1 GHz.
In addition, the impedance of your package leads has no bearing on the power decoupling. No amount of capacitace external or internal to the device will have any impact on the bounce that will be caused by power lead inductance. The only cure for that is a new package.
This is not borne out by the facts. If you can get your hands on Richey's book I would suggest that it is a valuable addition to any library on SI and EMI. His volume 2 will cover EMI in more detail and I am looking forward to it.
Wow! If your design is not high speed and the edge rates are not very fast, then power distribution is not a big deal. But nearly everything in this paragraph is incorrect. Yes, power planes cost money, that is true. Now that I understand how simple it is to figure out how power distribution works, I would never use any of these ideas on a board where I needed good noise margin or had high speed signals.
BTW, I never said a high Q power plane pair is bad. Yes, it can create impedance holes at very high frequencies, but the alternative for your approach would raise the floor, not lower the ceiling.
Have you tried simulating any of this? I would like to know what results your methods produce. The question is not so much if a method has worked a few times for you, but do you *know* it is going to work before you build the board. Ritchey's method lets you *know* it will work right the first time.
So, you loaded up the LTSpice simulations I posted, right? That's not speculation. And no, you haven't lost the battle with a few tiny traces, the vias are the bad guys as they give you loop area.
frequencies >
inductances
So, you advocate decoupling the power plane without considering what effect this has on the IC? Why would you go to all that effort if the package you're stuck with prevents your efforts making any difference?
packages
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best, if
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difference,
I have different facts, look at the sims I posted.
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I see from this paragraph you may not have grasped the effect that the BGA package connections are having on the PDS design. As I said, the whole point of the exercise is to get good supplies on the IC, not the power plane. The plane capacitance has such high Q it's good to severel GHz, I reiterate that you can't benefit from this on the device. I suggest you look at how Xilinx themselves route the power to their Rocket I/Os on their demo boards. The power supplies aren't on planes. The connection between the PCB and the IC mean it's a waste of time, I suspect for these Gbit circuits they embed caps on the FBGA.
I'm not saying it's necessarily bad. But it's not a great deal of help ON THE SILICON. You've gotta get that HF energy through vias, bga balls, traces(maybe) to the device.
caps
LTSpice
Only a nutter would do this without thinking about it and running some simulations. So, take a look at my LTSpice sim posts.
Tell you what, why don't YOU download the simulator from Linear Tech's website and learn how to simulate what you suggest? Then you can prove stuff to yourself without having to go to expensive classes. :-) You might even want to simulate the stuff you learned at your class with a real world situation and see how much benefit you get. Let us know how you get on. Good luck, Syms.
) SIM up to 200MHz with a 100pF plane and two combinations of bypass capacitors. (Cap data here:-
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)
If there's anyone out there who has both the time and ability to run a simulation, I'd appreciate some thoughts as to why my simulation doesn't match up with Rick's classes. I'm trying to find a *huge* parallel resonance! :-) I'm also looking for the benefits of different valued caps, as opposed to just using the biggest value you can get in the package you use. Thanks, Syms.
OK, so I've found the resonance, I needed a giant plane of 10nF, and only 4 caps. The resonance went away once I put a decent number of caps in the circuit. Who has only 4 caps on a board 30cm by 20cm? I'm still looking for a design where mixing the caps is better than not. Cheers, Syms.
I pretty much came to this realization with the XCV2000E parts in the BG560 package for high density reconfigurable computing needs. There was nothing I could do to overcome the BG560 packages small via, trace and bonding wire inductance to make the parts stable. Only choice was to seriously derate them.
I've not any high speed boards - the last board I made had internal frequencies at 150 MHz, and an external bus at 75 MHz (overclocked in testing to about 240/120 MHz), so maybe I'm missing something that happens at higher frequencies.
Using a simple tool such as Murata's software, I looked at the impedances for different capacitors at different frequencies. To a fair extent, the inductance is determined by the package size (and the board vias and traces), while the capacitance obviously goes up with the cap's value. So choosing a 0.01 uF instead of a 0.1 uF cap increases the capacitance side of the impedance curve by a factor of 10, and leaves the inductive side unchanged. It changes the peak frequency, but I fail to see why that should make a real difference - it has the same or higher impedance across the frequency range. Given that the 0.1 uF type has lower ESR (being made of more parallel plates), I can't find any way in which the 0.01 uF is better. So as Symon says (unless I'm misinterpreting him), the best arrangement is to pick the smallest size package you can conveniently mount (0603 for us), then the largest capacitance value you can conveniently and economically get in that size (100 nF), and use as many as needed for the board. Placement should be close to the device where possible, but is not very critical as long as it is within the range of the mini power plane (i.e., polygon on a signal layer).
It works for me - but then again, I'm not doing really high-end cards.
Better than what? If it meets your requirements, then you are done.
Your simulation was for two caps with no power plane, right? That is not a useful simulation.
A quiet plane is part of the solution. If your package produces ground bounce that blows your noise budget, you have no hope of building a good design. If so, you need to get a part with a better package. I don't get what you are saying.
Ok, is this conversation coming to an end? I don't want to argue about this. Your simulation was for two capacitors if I understood correctly. That has no bearing on the problem of power plane decoupling. Without simulating the power planes you aren't simulating anything useful.
Yes, you need to consider the package inductance. But you can't expect the power plane to fix a problem with the package. You can analyze them separately. The power plane will have noise from the effects of all chips on the board. The chip package inductance will only affect that one part. So analyze how much noise each will contribute and do what it takes to stay within your noise margin. Beyond that it is not useful to analyze them together.
Any noise you have on the power planes will add to the noise that the silicon sees.
Are you thinking of simulating with the power planes?
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