Typos in AD9901 datasheet?

I'm not sure about your questions, you can just switch the ref and var inputs in any case...

But I did want to point out that this phase detector is unlike most other digital freq phase detectors in that it generates a 50% duty cycle when in lock. This means you will have a large reference frequency component (or 2x the ref component ??) that will be difficult to filter out unless your comparison frequency is very much higher compared to the loop band width. Most other phase freq detectors output a small pulse when in lock which has a very small ref component and are easier to filter. The advantage of this XOR type phase detector is that is has no dead zone or dead band which some of the conventional ones can have.

Mark

I'm a bit confused by a couple of things on the AD9901 datasheet:

Rev. A -

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Rev. B -

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Firstly, in the functional block diagram in revision B, the logic symbol used for the exclusive-OR gate appears to have a blob on the output - making it an exclusive-NOR; however, I think it should be a plain XOR - as it was in revision A. On page 6, it says: "Near lock, the frequency discriminator flip-flops provide *constant* HIGH levels to gate the XOR output to the final output."

Also, aren't the captions the wrong way around on rev A figs 3 and 4, and rev B figs 5 and 6? Surely, the output duty-cycle exceeds 50% when phi-out (VCO) lags?

Can someone put me right on the above?

TIA Andrew.