Hello, I have a problem with peforming master dma with the xilinx pcix core. I'm writing into the systemy memory with 4KB blocks and I use a
4KB-BlockRAM in the FPGA as prefetchable datasource. The BlockRAMs have a read latency of one clock cycle. If I increment the internal source-address-counter with m_data_nxt, then the first piece ofdata comes out one cycle to late. The Design Guide says that the first piece of data must be presented to the core with assertion of m_attr_vld
and the subsequent pieces with m_data_nxt. I thought that this mechanism
can compensate the read latency of the BlockRAMs. But it looks like the first piece of data is NOT sampled with assertion of m_attr_vld. Who knows about the problem, when is the first piece of data samlped? greetings, Matthias