Using the top layer of PCB for voltages

What drawbacks are there to using the top layer of the PCB for voltages? I'm considering this because...

- The top layer doesn't make for much of a routing layer anyway.

- With multiple voltages (+24, +5, +3.3, +1.5) on the board the voltage layer, wherever it is in the stackup, isn't a very good plane to use as an AC return since it will have 4 islands that signals on adjacent routing layers would need to avoid crossing the unavoidable cutouts.

- The next layer down in the stackup would then be a ground plane so this start to the stackup would seem to make an ideal plane capacitor that is as physically close to the actual components as possible to minimize via inductance in feeding current to the components (assuming top side mounting only).

I'm guessing that there may be some manufacturability concerns since there are a bunch more processing steps for the outer layer but since the voltages won't tend to need narrow traces maybe there really aren't any. This PCB will have some BGA components, at the moment it looks like 1mm pitch.

Thanks in advance for your comments.

KJ

Reply to
KJ
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You are correct.

Depends on the number of layers. Usually you put the ground and power planes on the outer layers of a 6 layer board because the prepreg that is used between the top and internal 1 layers is very thin, 5 mils or less, and this gives you a useful capacitance between the planes. If you put the planes on the inside of the board, there could be 20 mils or more between these layers, negating any benefit of internal capacitance. So putting these on the outside is good as you pointed out.

You need to talk with your PCB fabricator and discuss the stackup of your board. Stick to what he usually does for the number of layers you need.

2nd, if you use the HDI approach of blind vias, you can effectively connect all your ground pins to the top copper and your power pins to the second layer with the blind 1-2 via. This reduces the swiss-cheese effect, especially on larger BGA packages which typically use half their pins on power and ground. This frees up the internal layers so you can actually reduce the number of layers needed.

Google for HDI (high density interconnect) and names like Happy Holden, Micheal Fitts. Email me if you need more info or some useful PDFs.

Reply to
a7yvm109gf5d1

(snip)

The top layer (component side layer) is the only one that can be connected to without vias. That makes it a pretty useful routing layer for me.

That said, I see no reason you cannot use all the layers as they best fit your purposes.

Reply to
John Popelish

Que? I think you mean to put the power planes in 2 adjacent layers in order to get maximum capacitance.

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Reply to
Nico Coesel

Outer layer and internal 1 are adacent. Internal 1 is what my fabricator calls layer 2. You can get maximum capacitance with lowest inductance only if the seperation is 5 mils or less, and this pair is on the outside as the OP suggested. On my example 6 layer PCB, it happens that the outer and inner 1 are built up on 5 mils prepreg. This depends on the number of layers and the fabrication process, this is why he should ask.

For example, using a 5 mils prepreg on the bottom of the 6 layer board gets you a nice snug fit between bottom and inner 4 for good internal capacitance, but if he places parts on top he'll have to access that charge using two vias 63 mils long each (or whatever the thicknes is. Point is, it'll be longer than going directly on top). This will resonate. It will limit effectiveness of the design. Put the planes where the parts are, put a thin prepreg, and use blind vias. It'll still resonate, but probably at a much much higher frequency where it doesn't bother us so much.

It's not that expensive and you can place more parts per surface area making more boards per panel. You can end up with a not-too-steep price increase vs. traditional, crappy through hole designs.

Reply to
a7yvm109gf5d1

Same for me. Actually I typically do signals on top and bottom layers only, the inside layers are planes - some cut, others not.

Here are some examples:

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- top,
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- bottom, 6 layers total.

Here is a larger one:

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(six layers again),

and here an older one (1999 or so), demonstrating me being rude enough to leave out not connected BGA pads to have some more space for routing signals... (never had a problem out of that, BTW):

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- top,
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- bottom.

Dimiter

------------------------------------------------------ Dimiter Popoff Transgalactic Instruments

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John P> > What drawbacks are there to using the top layer of the PCB for

Reply to
Didi

Well, feeding the power directly from the same plane certainly gives lower inductance, but if you have a dense board, you are unlikely to get sufficient area to move large amounts of current on the top layer. Whether this is an issue for you depends on the current draw (and especially the delta currents).

My solution is to put a power plane on the component layer (especially for BGAs) and punch to it through vias (lots of them) from a power plane for high current devices. As the next layer down is almost always a ground layer in my designs, I get the distributed capacitance. I would give a caveat about the statement about the relative thickness of the prepreg - just how thick that is depends on my impedance requirements - I have had prepreg to the outer layer be the thickest part of the stack on 16 layer boards and up. On low layer count boards [< 8 for an arbitrary count] that don't have impedance controls the outer prepreg is, however, usually quite a thin layer.

As John notes, the outer layer is also the only routing layer that requires no vias. The outer layers are incredibly useful for via-less breakout for highspeed signals (or any signal for that matter - every via you add costs money).

See my note about managing to get a suitable chunk of copper on the outer layer on a desnse board for power routing. No problem once you are at the point of load, of course - on BGAs (many times) the power balls are all together or at least close by. That, however, is _very_ device dependent. The issue is really getting that energy _to_ the point of load. Keep in mind that longer runs lead to more inductance which can play havoc with EMC to say nothing of local decoupling. A nice solid plane is preferable for high current / highspeed device feeds.

Blind vias are a very expensive option, although they are great if that's the only way to meet the requirements. 2 extra layers is usually _much_ cheaper than blind vias (to say nothing of the issues you'll put your layout people through). I've managed 16 layers in 2.4mm (0.95") with 10 impedance controlled and it was cheaper than 14 layers with blind vias. (It's the impedance controls that limited the number of layers to 16 in that thickness).

As to the outer layers; once we're all done routing, anything left is usually flooded and stitched to ground for a nice shield.

Cheers

PeteS

Reply to
PeteS

And it's a bear to kluge inner-layer traces.

We plan FPGA pinouts so that a lot of routing to other devices can be done on layer 1 with no vias or crossovers at all. That looks very nice. I have one board with 12 40 MHz, 12-bit ADCs dumping their data into one BGA fpga with no vias or crossovers. I let my pcb layout guy assign the FPGA pins and then compile around him.

John

Reply to
John Larkin

On 17 Oct 2006 10:52:46 -0700, Didi wrote in Msg.

This looks as if you solder the BGA directly on top of the vias without using the usual "dog-bone" thing on the top layer. Does this work well?

robert

Reply to
Robert Latest

Hi Robert,

yes, but there is an important detail (which I discovered the hard way). Basically, the solder balls remain stuck to the BGA chip while liquid, we all know how a drop of solder can hang on the tip of a soldering iron, no problem out of that. However, sometimes some balls - I have had up to 3-4 per BGA - come coldly attached to the BGA package, and when you reflow, they just flow down the via... My remedy to that is the obvious one - I reflow all BGA packages with some reasonable amount of flux once balls up, after that I have never had balls willing to get detached :-).

Dimiter

------------------------------------------------------ Dimiter Popoff Transgalactic Instruments

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Reply to
Didi

'Typically' my primary need for multiple voltage layers on a PCB was because there was no good way to get the various voltages to the devices that needed it without resorting to convoluted cutouts that necked down unacceptably. It wasn't so much of a problem of current draw itself, it was current draw and the narrow passageways that would be needed. So by using multiple voltage layers I could avoid the narrows.

Assuming that the same holds true on the next design, it might be handy to use the two surfaces of the PCB as the first two voltage layers, with the component side surface being used for those voltages that have the highest dynamic current requirements. My post about only using the top surface was a bit of a simplification since I think this would be the more stringent case and I didn't want to overcomplicate my basic question.

Where I was sort of going on my post, was assume you know you have multiple voltages (4 in my example) but let's just say that where they fan out to leaves nice wide areas between source and load so steady state current draw is not an issue. Although 'nice and wide' to deliver the requested current, there will be 4 distinct islands where use of this voltage layer as an AC return path will not be acceptable so in many cases you just can't use the voltage layer as being the layer adjacent to a routing layer because of the big ground return loop you would create.

And if the top surface can't be designed to deliver the power then I agree. However, each of the internal power planes are still swiss cheese giving up a significant amount of their plane area (assuming that the BGA balls fans out to a via). The top surface is 'slightly' worse in that in addition to the swiss cheese of the vias there are also those traces from BGA pad to via that need to be kept away from.

I say 'slightly' in quotes because I'm sure it's more than 'slight' and would have to work out the math to see how much plane area gets lost due to avoiding those traces which is a function of the BGA ball spacing and the line widths/spacing. But knowing how much additional plane area gets lost due to avoiding the surface traces you can analyze and tradeoff to see which would give you the lower impedance path for the voltage to get to the part. Just wondering if anyone had done this before and how it worked out.

Agreed, I shouldn't have said 'nearly useless'. It has definite uses.

Yep, and FPGAs tend to have more than one voltage just to make it worse.

But if you have those through hole vias on your BGA breakout to get to a routing layer, than you don't have anything near a solid plane either.

I do that as well but was thinking that flooding the surface with voltages with ground on the next layer down might be better in some cases to avoid the problem of the cut up voltage layer. The top layer doesn't become a Faraday cage, but as long as darn near all of the actual routing is internal, than the second layer ground would be a cage.

KJ

Reply to
KJ

Well, I noted (very tangentially perhaps) that much depends on tyhe current to each destination :)

I understand that. I have indeed done what you are looking at, but there's a tradeoff (which I may as well look at now).

The 2 basic things that have to trade off are:

Power impedance to the point of load Desirability of via-less breakout

The last time I did a very highspeed board (96 5Gb/s pairs on a single BGA, two of those on each spine board) via-less breakout was _very_ desirable, for as many signals as possible. As John notes, it's also nice for those signals that are otherwise particularly susceptible to deterministic jitter and impedance mismatch (fast A-D is, of course, a prime example).

If you don't have those issues, then go ahead and use vias for breakout, but you'll have a hard time getting the power to the centre pins through there :)

I have never been able to successfully route a power layer completely on the surface to a BGA with power at the centre (the usual state of affairs). With 1mm ball pitch and (usually) 0.4mm pad width, you have

0.6mm free. If you break out _everything_ through dogbone style pads, you will have that 0.6mm, but you have to maintain a clearance, obviously.

Given the mess that makes, I have simply found it much simpler to route the power on an inner layer and then punch up at the centre of the BGA.

I understand the issue about the cut-up power plane - that's an issue we all face in most designs nowadays.

The best advice I can give is look at the option of surface vs. inner (given the current and pin/pad clearance requirements) and choose the one that works best.

Cheers

PeteS

Reply to
PeteS

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