Multiple PicoBlaze/Bus access

My design has 2 PicoBlaze processors on a Spartan-IIE sharing a common IO bus (PORT_ID, IN_PORT, OUT_PORT, READ_STROBE, WRITE_STROBE). I am planning to use simple priority based bus arbitration. Now I am trying to figure out the minimal changes I need make to the PicoBlaze core in order for the IO logic to be bus aware. It needs to assert BREQ to request the bus, wait until BACK, use the bus, then deassert BREQ to release the bus.

Any suggestions are most appreciated. Any resources I can look at?


- Abdul

Reply to
Abdul Nizar
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If the bus is simple (as in a single cycle per operation), another approach is to alternate between CPUs and make each CPU stall if it needs the bus at the wrong time.

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Reply to
Hal Murray

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