Austin Lesea wrote
Jim,
>
> We can keep the memory contents of the 4VLX25 all the way down to where
> the configuration logic recognizes a power down condition (runs around
> ~0.6 V).
>
> Now, to be sure, we have not characterized everything down that far
> (0.6V), but we did do all characterization for functionality tests from
> 1.0V to 1.4V, so we know for sure we are safe inside this region (memory
> contents stay). If someone had a killer app that needed beaucoup parts,
> we would consider binning for lower numbers.
>
> Some people are considering operating at the 1.2V nominal, and then
> 'sleeping' at 1.0V. The sleeping is just all clocks stopped (disabled).
On this subject of lowering FPGA Vcc's to a keep-alive level / hibernate, this is a new device from Linear
formatting link
It has an i2c BUS + 6 bit DAC, which covers 0.85..1.55V on Core, plus two Aux LDO paths.
-jg