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What limits noise in voltage regulators?

Mostly at higher frequencies, above the useful range of frequency response in the feedback loop. I saw a board design that used an op amp and an n-FE T as a linear regulator. The power source to the pass FET was a switcher t o prevent a lot of dissipation and the op amp was powered from the 12V inpu t so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configuratio n there was no gain other than the op amp which has a 1 MHz gain-BW product .

So in the frequency range above 100 kHz say, I would expect the control loo p to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Raisin g the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the so urce rise... however, that is without considering the FET capacitances.

The gate-source and gate-drain capacitances will bring the gate up to allow the drain noise to transfer through to the source. Is there a reasonable way to mitigate this effect? Someone suggested adding capacitance to the g ate to swamp out the effect of the gate-drain and gate-source capacitances. If that can be done without impacting the response of the control loop, i t seems like it might work. Or is this doomed to fail because it *will* im pact the control loop at a level before does what is intended?

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Rick C. 

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Reply to
Rick C
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Usually, a regulator can be made quiet by an output capacitor. If stability is more important than accuracy, you can downsize the output capacitor and just use a slow op amp and transistor follower. Bipolar transistors have nicely low output Z as long as they're driving significant current, and a base capacitor gets capacitance-multiplied.

Reply to
whit3rd

What happens to stability when you add the cap to the base? Why would this not work the same for a FET?

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Rick C. 

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Rick C

In the old days open loop voltage regulators were often used, i.e. an emitter follower driven by a constant voltage at the base, The base voltage is just Vbe drop higher than the desired output voltage and typically generated by a zener diode, thus no feedback.

The transistor fT determines how well the output noise follows the base noise at higher frequencies. The low power base circuit noise is easier to suppress than the full power output noise.

The bipolar Vbe drop is quite well defined, thus the output voltage is quite predictable. Open loop regulators work better with higher voltages, but usually the variations of Vbe is too large for 3.3 V and lower output voltages, requiring a feedback construction.

Reply to
upsidedown

snip Having a base cap and an emitter cap /may/ create a parasitic colpits oscillator.

Reply to
Rocky

A bipolar transistor emitter has lower output impedance than a MOSFET source, in follower connection. So, it regulates output voltage better with current-drawn variations, at frequencies above effective feedback control.

Output impedance = dV_{be}/dI = 0.025/I at room temperature (from an Ebers-Moll model) so at 200 mA, it's about 0.13 ohms.

Reply to
whit3rd

Use a BJT, or two in series. My go-to is a single stage, two- or three-pole cap multiplier (two or three RC sections in the base), one in the collector (might as well use that V_BE drop for something useful) and one at the output. You can get sub-nanovolt noise densities that way.

Of course there's not a lot you can do at very low frequencies but buy a quieter reference.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs
[...]

A handy trick is to stand up a general purpose regulator on a diode or two to get a slightly higher output voltage, then use a long time-constant RC network to remove the noise down to whatever lowest frequency you need. Feed the Base of a low noise audio transistor from the quiet supply, power the Collector from the slightly-higher stabilised rail and take the load current from the Emitter (as an emitter follower).

The stabilisation with variations in load will be poorer but the L.F. noise level will be excellent. I have used that circuit for feeding electret mic capsules.

It also gives you the option of referring your low-noise supply to a signal earth (or even a wanted signal source) at the bottom of the capacitor, rather than a power earth which may introduce extra noise.

--
~ Liz Tuddenham ~ 
(Remove the ".invalid"s and add ".co.uk" to reply) 
www.poppyrecords.co.uk
Reply to
Liz Tuddenham

You can just hang a giant polymer cap on a regulator output. It gets better as the regulator loop gets worse.

Or, as someone mentioned, make your own regulator with a well-filtered reference and a good opamp. Some linear regs include a reference bypass pin.

Bypassing the adj pin of a 3t reg often helps too. Or bypassing one feedback resistor for the other kind.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

nse in the feedback loop. I saw a board design that used an op amp and an n

-FET as a linear regulator. The power source to the pass FET was a switcher to prevent a lot of dissipation and the op amp was powered from the 12V in put so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configurati on there was no gain other than the op amp which has a 1 MHz gain-BW produc t..

loop to have minimal impact on noise from the switcher. However, even thou gh the FET configuration has no gain from gate to source, it should have ga in to minimize the transmission of noise from the drain to the source. Rais ing the drain voltage will increase the current raising the source voltage. Of course that reduces the gate-source voltage which acts to prevent the s ource rise... however, that is without considering the FET capacitances.

llow the drain noise to transfer through to the source. Is there a reasonab le way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacitance s. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *will* im pact the control loop at a level before does what is intended?

'one in the collector', scratch scratch, scribble... Where does the collector RC go? anywhere I put it looks to increase to resi stance (power supply source resistance) of the cap multiplier.

George H. (who needs to start a thread on higher current cap mults. with either a Darlington or Sziklai as pass element... but I need to order some transistors first.)

Reply to
George Herold

Adrian, you need to keep your alter ego for the weekend. ;)

I occasionally put the cap multiplier inside the DC feedback loop of a regulator, with AC feedback taken from the collector circuit so it doesn't oscillate. Cheap shunt voltage references tend to be very noisy, and the Zout of an emitter follower is pretty low, so I usually just hang the cap multiplier off an LM1117 or a switcher.

Discrete circuits can have wonderful properties, but good supply rejection is not one of them. Cap multipliers fix it.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

Biasing a photodiode off a switcher rail requires like >150 dB of noise rejection. A cap multiplier can do that, if you give it some help in the collector circuit, but a single bypass is not going to get you there. (Well, 150 dB will probably take two transistors, I admit. You also have to be insanely scrupulous about layout.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

Salient point! Just beware of the reverse, too. If you're trying to avoid massive supply current spikes being passed through from the load, you can't do that with a big load-side capacitor if your regulation is tight. The regulator just sees the cap voltage drop and opens wide to replenish it.

CH

Reply to
Clifford Heath

You've got a whole V_BE to play with in the collector circuit before you run into any trouble, so you pick the resistor to drop maybe 0.4V at max current, and size the cap appropriately. You can also use an LC.

In my Class H TEC driver, I use an all-reactive cap multiplier, which also works very well.

Sziklai for my money. Local feedback is almost always a win.

(The switcheroo Wilson current mirror [not the usual Wilson] has three feedback loops made from four components total.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

For low DC currents, a few stages of RC filtering is pretty good.

150 dB is kind of demanding. That might need a can, and some exotic ground planes, stuff not on the schematic. 
--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

Yup. Round here we mark places on the schematic that will need super-good isolation with a pink highlighter, so it's called 'the pink treatment'. Faraday cage, blind vias, multipole filtering, minimal loop areas, tight restrictions on what can be on the back side and what traces can be routed through the area (even on the other side of the featureless ground plane), and a can over the whole works. (Lotsa via stitching on the mounting pads for the can, too.)

We had one PSU board with a 1.5 MHz async buck switcher making -17 from an intermediate +12 rail.(*) It was supposed to be an AOZ1280, but in reality was a Chinese counterfeit that the CM had in stock.

Parts of that board showed a whole lot of 125 MHz junk, and other parts almost as much junk but at 180 MHz. Turned out to be harmonics from that buck switcher, selected by transmission line resonances in the board. They got into everything that was powered off that intermediate rail (i.e. just about everything).

Turning off the negative reg cleaned the whole board right up.

Cheers

Phil Hobbs

(*) The +12 was needed because the negative reg's voltage rating wasn't high enough to make -17 from +24 directly. It was made by an LMR23630 sync buck, which is a very nice part if you watch out for the ~600 ps edges.

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

We don't often hang around the noise floor. We usually have enough electrical or optical signal to break things. One place we do have problems is time jitter. Switchers and picosecond jitter don't co-exist well on a board.

"Demodulating time" can extract the jitter component, and the recovered frequency hints at the source of the wobble. HP once had an instrument to do that. One trick is to use a sampling scope to look at an edge, zoomed way up, and vary the system trigger rate. What looks like noise can sometimes be heterodyned and revealed to have structure, then one applies some simple number theory to relate it to one of the switchers on the board. Or touch/spritz each switcher to see which one is the cause.

I had one LTM8078 switcher making jitter that was so close to 200.000 KHz that I was sure a crystal oscillator was involved. It wasn't.

I have this problem often enough that I should build a time-to-voltage converter probe somehow.

Some synchronous switchers make insane edges.

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Looks like a drift-step-recovery substrate diode to me. It freaked out opamps 6 inches away.

The little LTM bricks seem to keep most of that sort of thing onboard. I think TI has some similar switcher blocks now, with the inductor and some capacitance included. That helps with ground loops.

I sometimes put nasty circuits on mouse-bite subassemblies.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

ponse in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switch er to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was t he same as the output voltage, so with the FET in a common source configura tion there was no gain other than the op amp which has a 1 MHz gain-BW prod uct..

ol loop to have minimal impact on noise from the switcher. However, even th ough the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Ra ising the drain voltage will increase the current raising the source voltag e. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.

allow the drain noise to transfer through to the source. Is there a reason able way to mitigate this effect? Someone suggested adding capacitance to t he gate to swamp out the effect of the gate-drain and gate-source capacitan ces. If that can be done without impacting the response of the control loop , it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended?

in

ay.

a

Right, I used a cap mult on the end of a supply for biasing led's for shot noise measurements. Switching supply, LC lowpass, Voltage Reg., cap mult. My big mistake was not paying enough attention to the noise in the voltage reg. It was the biggest noise source into the CM. Later design replaced Volt reg, with volt ref and opamp. (w/ RC stages between reference and opamp.) George H.

Reply to
George Herold

The minimum achievable is going to be related to the reference and regulator components along with their layout and environment - so a low frequency issue that can't be addressed with filtering.

The active components can also be affected by HF modulation as well, so shielding and placement of noise sources also has to be considered.

As peak and random deviation are time-related, it will also be dependent on measurement technique. Measuring equipment obviously has to be quieter than the thing being measured, so toss your digital scopes, multiplexed dataloggers etc etc etc. . . .

RL

Reply to
legg

ponse in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a switch er to prevent a lot of dissipation and the op amp was powered from the 12V input so there was plenty of drive to the gate. The reference voltage was t he same as the output voltage, so with the FET in a common source configura tion there was no gain other than the op amp which has a 1 MHz gain-BW prod uct..

ol loop to have minimal impact on noise from the switcher. However, even th ough the FET configuration has no gain from gate to source, it should have gain to minimize the transmission of noise from the drain to the source. Ra ising the drain voltage will increase the current raising the source voltag e. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitances.

allow the drain noise to transfer through to the source. Is there a reason able way to mitigate this effect? Someone suggested adding capacitance to t he gate to swamp out the effect of the gate-drain and gate-source capacitan ces. If that can be done without impacting the response of the control loop , it seems like it might work. Or is this doomed to fail because it *will* impact the control loop at a level before does what is intended?

in

ay.

resistance

Sorry to be so dense, but you're running the R from collector to emitter,(?) with an emitter cap to ground?

I must say that a resistor across the transistor seems like the wrong thing to do...

George H.

Reply to
George Herold

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