internal interface on chip network


In on-chip network, we need a network interface (which may contain switch, router, queue, etc) for each processing node. I am considering MESH interconnection and Xilinx FPGA implementation.

I want to design it in hardware, so looking for resources (reading material, previous work, examplary HDL code). And it is cloudy and no idea.

Which routing algorithm, which switching scheme (address en/decoding), what should I consider more....and so on.

Could someone kindly guide for this work....thankyou

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