Run SDRAM with slower speed

You must look at the data sheet for the specific part, to be sure.

Some SDRAM modules include clock distribution chips that can only run over a narrow range of frequencies.

Bob

Might add here that even if you can scale the clock, you can NOT scale the refresh interval.

Tam

Besides the issue with clock distribution. You must make sure that you have sufficient time to refresh all bits.

This is clear from the datasheets, but one thing that was not at all clear when I was looking at this is how the length of a self-refresh cycle scales at lower clocks. e.g. the Micron MT48LCccMxA2 series data fig.37, the time taken for auto-refresh is shown as min 66ns for the -75 speed grade based on 10ns clock, but it does not indicate how many (if any) clocks are required at lower frequencies.

This is an issue for design I'll be doing soon & I'd be interested if anyone has any info on this.

"eeh" ...

We use 133 MHZ chips at 44.32 MHz. Tested at exterme temperatures. No problem. Just keep the proper refresh time.

Arie de Muynck

when I was looking at

the Micron MT48LCccMxA2

the -75 speed grade

required at lower

has any info on this.

I'm currently working on a similar design with the MT48LC series, and self-refresh is a key feature. Bit-banging with a slower MCU, it's critical to keep from burning a lot of cycles doing refreshes.

According to the datasheet I've got (pg.13), "The Self Refresh command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. ... all the inputs to the SDRAM become Don't Care..." This is reinforced by the Self Refresh timing diagrams (p.40).

To the OP's question - it'll depend on what kind of SDRAM you're using. SDR SDRAM appears to support very slow clocks. OTOH, DDR and above have minimum clock speeds, virtually requiring a DRAM controller (which these days is hard to find as a separate part.

Richard

when I was looking at

the Micron MT48LCccMxA2

the -75 speed grade

required at lower

has any info on this.

Sorry I meant auto-refresh, not self-refresh....

Maybe one can accomplish this with an fpga? (if it's below 200 MHz at least..)

I was looking at

the Micron MT48LCccMxA2

the -75 speed grade

required at lower

has any info on this.

Follow-up - I have just had confirmation from Micron that there is no minimum number of clocks required during the auto-refresh cycle, you just need to meet TRFC, so for example at 25MHz, TRFC is satisfied after 2 clock periods

Yep. Adding an FPGA would be the next step, though I have to think it'd be cheaper to move to an MCU with integrated DRAM controller. Then again, the FPGA might be handy for some other high-performance transfer operations.

I looked briefly down this path and was also deterred by the tool limitations / startup costs.

For the moment, SDR DRAM looks to have a good life left in it.

Cheers, Richard

If you just want a SDRAM controller, You may also want to look at some CPLDs - e.g. XIlinx 95xx series. Parts are cheap and supported by free ISE tools from Xilinx.