Issues on Shift Register in a Clockless UART

Simple answer: You cannot. You can of course generate your own clock... Peter Alfke

it should perhaps be pointed out that UART's aren't in fact clockless.. they are self clocking... that is the clock is passed with the data (i.e. the leading edge of the start bit is the re-syncing edge)

Simon

The LIN Bus takes this a step further, in that a BAUD rate is not assumed, but they send a known preamble byte (55H or AAH IFW), and that allows 'floor sweepings grade' uC / RC osc to autobaud.

No reason the same ideas could not be used on a FPGA.

You would start a low precision burst oscillator on the leading edge, calculate your AutoBAUD divisor on the first byte, and run until a known stop char/count, then go back to clockless-sleep.

Rather high baud rates would seem to be possible...

-jg

But this is not "clockless". If the OP really means a UART using *no* clock, I don't see how this can be done. Sequential logic can be made that does not require a clock, but a UART must have a clock to measure time. The UART data format provides information on the timing of the start of a word, but you still need a clock to measure the bit times.

You could have a huge delay line with taps spaced at the center of each bit period. Latch the taps' output with the stop bit. I'll get me coat.... Cheers, Syms.

I would call that self-synchronizing, not self-clocking. Manchester code is self-clocking, provided you get it going "on the right foot". Peter Alfke

I would agree ... and stand corrected ... but can you always think of the right words ... :-)

But I did point out that you re-sync... that implies something... and I believe the delayed shift register (mentioned in this thread) has already been done but that also requires a clock. and so I think most people have seen an "AT" modem.. re auto baud.. Hayes and stuff like that .. even they have clocks. FPGA's are synchronous.. so is a UART. All comms is synchronous or synchronised. (unless its simply on and off!)

Simon

they

It becomes an exercise in semantics : Uarts require triggered, time interval sampling. You _can_ build a uart without an external, precision, always on clock source. To some, that qualifies as 'not using a clock'. Others might say any digital-divider must have a register, and that register must be clocked, so all registers are verboten in a purists 'Clockless uart'. That design can be done with a delay line ( which needs baud-precision

- not really a common building block...), plus it's not clear how it would manage sync in packed streaming data...

Complex Async ICs design is not truly clockless, but it can be self-timing, and not locked to a common bus'd clock.

The OP's question sounded rather like homework, than any real problem needing a practical solution....

-jg

on

Say... Do you mean an "asynchronous" UART? You *do* have a system clock available to the FPGA, right? Something in the MHz range?

(in answer to a question about a clockless UART)

Someone I know used to have a paper tape reader that you would pull the tape through by hand. A row of phototransistors and LEDs would sense the holes as they went by, including the row of clock holes.

I had wondered about making a card reader using a similar design, but there are no clock holes. It would be necessary to either run the card at a constant speed, or otherwise measure the speed or position of the card. A rubber wheel and phototransistor/LED sensor to read its position should be enough.

Paper tape is self clocking but punched cards are not.

-- glen