Simple TTL electronics question (On-Topic in other words! Sorry!!)

I'm looking at replacing some I/O 40 pin chips that are quite obsolete (R6530 by Rockwell). In the circuit I'm replacing these were used for their two 8-bit I/O ports (amongst other things) and I was thinking that as the ports are never changing direction that I could simply replace these device's ports with TTL 8-bit latches.

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Any reason why not?

Speed is around 1mHz so not a factor.

Thanks! John :-#)#

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Reply to
John Robertson
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No. The device has other internal capabilities that the latches won't emulate (the ROM, RAM and TIMER).

If you can guarantee that none of these are being used (which would be unlikely in a pintable/video game) *or* emulate them, as well, then the latches CAN be used to emulate the PIOs.

You would also need to evaluate the loads to which they are connected (esp Ioh) to ensure the loads are adequately driven.

Reply to
Don Y

on't

I've dealt with the timer and ROM/RAM already.It was just the I/O that I

was curious about if there was anything I might have missed. Loads, yes,

sufficient drive is just the usual TTL (not LS) specs. The device I'm replacing this with isn't using the TIMER nor the /IRQ, making it pretty

easy to emulate.

John :-#)#

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Reply to
John Robertson

The Rockwell device also lets the software "read-back" the values that it had previously written to the data (output) latch. So, without knowing if the software relies on that capability, you may find that attempts to update one or more *individual* bits -- by reading the previous contents, masking off the appropriate bits and then merging the new bits, before updating the latch -- will fail in unpredictable fashion (reading back data from your latches will result in a read of a "floating bus").

E.g., if the bits controlled 8 discrete loads and you wanted to turn OFF load #2 -- without altering the state of loads 0 through 7 -- you would read the output latch to get the current state of those other bits, apply a mask to ignore the old value of load #2, merge the new desired state of load 2 into that value and then update the latch.

If your "read" of the hardware latch returns random "bus noise", then you will interpret that as the state of the other loads and then deliberately *make* it the state of those loads via this operation!

If, OTOH, the software preserves copies of the last written value in RAM, somewhere, then it will likely work -- it will never look to the hardware for that information.

[Or, if the latch is used to store WHOLE "bytes" and not "sets of bits".]

Motogorilla and Intel made comparable devices. You might see if any of those are drop-in replacements (Moto's devices had similar bus timing to the 6500).

Reply to
Don Y

won't

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That is an interesting point. We are disassembling the code and will look for that.

Appreciate the info!

.]

Again, hopefully the disassembly will prove this one way of the other. I

hadn't considered it previously..

ny of

o

Yes, the 6821 is very similar to the 6520 (drop in sub usually) but not so easy on the 6530 perhaps. Need to read up on it a bit more.

Thanks again,

John :-#)#

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(Please post followups or tech inquiries to the USENET newsgroup) 
                      John's Jukes Ltd. 
MOVED to #7 - 3979 Marine Way, Burnaby, BC, Canada V5J 5E3 
          (604)872-5757 (Pinballs, Jukes, Video Games) 
                      www.flippers.com 
        "Old pinballers never die, they just flip out."
Reply to
John Robertson

I've succesfully re-created similar devices using ATF150x CPLDs.

5V logic, plenty of speed, still in production and can be often made to live in the same footprint as the original IC (although I had to route a 4 layer board sometimes). The only drawback is that sometimes 32/64/128 macrocells aren't enough. I prefer to use 2 x 32 macrocells CPLD instead of a single 64 one since 2 of the smaller ones can still sit in the old 600 mils DIP footprint. Not terribly out of time too (they are just fat PALs, in some ways...)

just my two cents.

Frank

Reply to
frank

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