Hello,
I'm new to the world of CPLDs or FPGAs so please be easy on me. We have a requirement for an 8 channel (12 channel would be better) countdown timer at 12 to 14 bit resolution with a 20MHz clock input.
All we need is to be able to load the channel's timer value via the processor's data bus and start the timers after the last channel is loaded. We need 8 (or 12) outputs that go high during the countdown and turns off when the timer times out and stays off until the next time they are loaded.
Is this possible in a relatively cheap CPLD and which "family" would be a good starting point? If this is a complicated design we would certainly entertain the possibility of farming this out.
Thanks,
Richard