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Instantiating an lpm dcfifo in Verilog

Hello, I know many will say this is not an appropriate group to post such a question, but I wasn't getting any response on the Verilog group, so please let me apologize. I am new to Verilog and need some help instantiating a lpm dcfifo in my code. Here is what I have so far:

FIFIN : lpm_fifo_dc WITH (LPM_WIDTH = 64, LPM_NUMWORDS = 64, LPM_WIDTHU = 9, RDSYNC_DELAYPIPE = 3, WRSYNC_DELAYPIPE = 3);

FIFIN.aclr = (!rstn); FIFIN.wrclock = (clk); FIFIN.wrreq = (wr_fiforeq); FIFIN.data[31..0] = (dma_wrdata); FIFIN.rdclock = (clk); FIFIN.rdreq = (dma1_rddata); FIFIN.q = (rd_fiforeq);

If anyone has some examples of instantiating a lpm function within Verilog I would greatly appreciate your help.

Thanks, joe

Reply to
jjlindula
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Hello, I believe this works:

dcfifo # ( .intended_device_family ( "Stratix II GX"), .lpm_hint ( "MAXIMIZE_SPEED=5,"), .lpm_numwords ( 64), .lpm_showahead ( "OFF"), .lpm_type ( "dcfifo"), .lpm_width ( 64), .lpm_widthu ( 6), .overflow_checking ( "ON"), .rdsync_delaypipe ( 4), .underflow_checking ( "ON"), .use_eab ( "ON"), .write_aclr_synch ( "OFF"), .wrsync_delaypipe ( 4) )

dcfifo_component ( .wrclk (wrclk), .rdreq (rdreq), .aclr (aclr), .rdclk (rdclk), .wrreq (wrreq), .data (data), .wrusedw (sub_wire0), .q (sub_wire1), .rdusedw (sub_wire2) // synopsys translate_off , .rdempty (), .rdfull (), .wrempty (), .wrfull () // synopsys translate_on );

Reply to
jjlindula

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