Impact of voltage variations on timings for an FPGA

JF,

As long as the voltage never goes below the min (1.425V in this case), noise included, all timing will be met (we guard-band the speeds files and do all testing at hot, and low Vcc).

If, however, the noise takes you below 1.425V, then you degrade the timing.

Additionally, noise adds jitter, which should be characterized (measured) which also reduces the slack.

Aust> Hi,

Hi Jean,

For Altera's FPGAs, the timing produced by Quartus will take into any internal voltage drops. So provided that your external Vdd does not drop below the minimum value spec'ed in the data sheet (for example, 1.425 V for Stratix/GX/Cyclone vs. 1.5V nominal), your timing report will be valid.

Regards,

Paul Leventis Altera Corp.

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