Are you saying the thermal dissipation isn't outrageously high, but the Vce(on) appears very high even so?
Make sure your oscilloscope isn't lying to you. When off the IGBT blocks a huge amount of voltage, but when on the voltage becomes very small. On the small scale needed to measure Vce(on) the oscilloscope may not work properly due to the extreme high voltage at other times.
Try measuring Vce(on) through say a resistor and a low voltage zener diode to clamp the maximum peak voltage to something small like 10V. Keep in mind the resistor plus zener and probe capacitance make a low pass filter which will degrade measurement bandwidth.
I'm currently using a pair of IGBTs in my prototype smps ( UC3525 controller - half bridge configuration with IR2110 driver ).
It's up and running nicely now after the kind help here.
I've been testing it with some dummy loads to check device dissipation and current waveforms ( just a large R across the bridge directly or coupled by a 1:1 TX ).
At a load of ~ 600W I was surprised by the temp rise in the IGBTs. Makes no difference if the load is transformer coupled or not btw.
Looking at the Vce of the lower device whilst on, I saw about 8V. According to the datasheet ( it's an Infineon SGW30N60 btw ) with the 4A or so it's carrying, Vce should be < 1.5V. High side device appears to dissipate the same. Temp rise seems to correlate with the heatsink thermal resistance ( 3C/W) and the calculated dissipation.
Gate drive voltage is ~ 14 V. Waveforms look clean to me.
Now the puzzling bit. I removed the big load but a small load ( actually
33k ) remains. Vce(on) remained at 8V !
It should be *very close* to ground. Any clues why not anyone ?
Device on-time is ~ 4 us and dead time ~ 1us currently.
That would have been tomorrow's ( today's now ) job. In fact I was thinking of swapping in a Mosfet with about 200~300mOhm Ron. That should certainly have illustrated any measurement technique error.
I don't think the part is damaged though.
Also just occured to me that if Vce is really 8V then Vboot for the IR2110 would be degraded by that amount too and I can measure that directly.
No, both figures appear fine and self-consistent. Figure 4 is for the DC case, which is more severely limited by temperature rise. Figure 1 (top trace) is for the peak current of a 50% duty-cycle sawtooth, as they show in the inset. The short peak duration allows for higher peak currents, especially if the frequency is above 1kHz (500us ramp, 500us off). Figure 2 is another look, tying these together. Of course all three assume Tc = 25C, which is impossible in operation, and Tj = 150C at the graph's max, to which you might be unwilling to push the part, so a severe derating would be in order when using any of these figures. Figure 16 (transient thermal impedance) also ties them together.
Figure 1 is a nice plot that's rarely seen, and gives a valuable result that's a bit hard to come up with on your own using the more common SOA and transient thermal impedance information in figs 2 and 16. To create fig 1, they'd need to have a fairly-complex well-tested thermal model, or take lots of rather painful measurements. I say painful, because it involves apparatus that the average joe, such as myself, doesn't have.
How are you driving the IGBTs? The gate resistor should be 11R, with a 3A schottky parallel for faster turn-off. The2113 driver is also better for FETs only, I would rather have a negative gate voltage for turn-off. What you see is probably shoot-through current because of the slow turn-off. Then 200kHz is way too high for IGBTs, this size stay below 40kHz. Look at the data sheet figure1.
It's all leaded parts and I used 1/4W rather than 1/8W here. Saw that one as a possibility at least ! I think I even modelled the series Rg dissipation even !
I have a fast diode ( not shottky ) in parallel. Where do you get the 3A figure ? Turn off looks very clean btw.
Understood, but this is what I have currently. Examination of a well-known product with similar design shows this to be adequate.
I've seen the considerably older IRG4PC50U used in exactly this configuration with zero problems.
Yes, I've looked at Fig 1. I don't expect Tc to exceed 80C ( I hope ). That would appear to be good for ~ 25A = ~ 3.7kW output. It won't be a continuous requirement on account of the nature of the psu ( high instantaneous peak requirement - lower average requirement ).
drop the switching frequency down to, say, 1kHz where you can completely ignore the switching losses (Lmag may need to be cranked up, or Vdc reduced to compensate).
thats a seriously crap Vce. there cant be too many reasons:
- measurement is wrong
- Vge is way too low
forget 1kHz, do it at DC - turn the bottom IGBT on, and slam some serious current thru it. Easy to measure Vce then, esp. when Vdc is low.
good point - scope thermal tails due to overdrive.....
i've built compensated dividers clamped with 4148s for this job.
bingo. kind of crap, but better than nothing. I forget the vendor, but a Tektronix spin-off makes beautiful broadband diff probes for exactly this job. $$$$ :(
If Rg was much higher than expected, Cge//Cmiller could cause the waveform to "average" out at 100kHz. winding Fs down would show that, as would a decent floating gate drive measurement. A tek P5200 would help..
another possibility is a nice big flat spot in the Vge waveform, where Cmiller fights with Rg. If you say use 0603 Rgs and them snot them with gate charging pulses they can go high.....
sometimes Pavg is an issue, but usually not until F is high or the IGBT is huge (100nF Cge anyone?)
Ppeak is more likely a problem, but 1/4W leaded Rs should eat a few tens of watts peak. if RgCge > Trise then Ppeak reduces too. the calc is easy, and spice is trivial.
fig. 14 shows Eon and Eoff both have similar slopes wrt Rg, so although a lower Rgoff has more effect than lowering Rgon, the difference isnt huge. Off delay is greatly reduced with smaller Rgoff though (but it only fiddles with pulse width, and has little bearing on losses)
With Rg = 0R, fig. 14 shows total switching energy Ets = 1.5mJ for inductive 30A load, so at 4A, 100kHz thats 200W. Hmm, thats pretty high. It fits with Bans comment re. fig 1 though - current wants to be pretty darned low at 100kHz.
I have played a few times (mostly analytically, a few experiments) with these so-called "fast" little IGBTs, at around 100kHz. every time a 600V FET won hands down, due to switching losses. To be fair I havent exhaustively tested little IGBTs, having given up after the 3rd or 4th try.
Vth worst case is 2V. Your gate driver output wont pull to 0V, the difference between the two is your noise margin. emitter-followers would not be a great idea here.
lets pretend Vgd = 0, then Cmiller has to force a 2V spike into Zg = Cg//(Rg + Lg). This is where Lg can get you into trouble. using a -ve bias means the noise margin = Vth + |V-|, allowing a much higher Zg.
Rg is low, but if the dV/dt is occurring in say 20ns, then Fknee = 16MHz = 100Mrad/s, and 10R == 90nH. your leaded resistor has 10-20nH all by itself, the gate lead adds another 10nH or so *as does* the emitter lead, then there is the rest of the loop, the IRxxxx bond wire etc.
admittedly a crude analysis, but the problem is real.
a simple test for cross-conduction is a small, low-inductance resistor (or A6302 current probe) at the bottom of your dc bus cap. look for the spike. Unfortunately this test can introduce enough inductance in the DC bus to over-voltage the igbt.
another, less-intrusive shoot-thru test is to crank the dead-time up, then measure light-load Tj as Tdead is slowly reduced (measure steady-state Tj, reduce Tdead, continue until bang). When cross conduction begins, Tj rises.
fig 1 is bullshit. For a start, fig. 4 shows a 40A DC current limit, due to bond wire alone. if its 120A 150C Tj then fig. 6 gives Vce = 6V, for Pon = 720W, IOW 360W average. yeah right. Then Ets = 4*1.6 = 6.4mJ, shown flat to 40kHz - thats another 256W switching losses. So P_avg =
600W or so. with a 70C rise in Tj? Rtheta_total = 70K/600W = 0.12K/W, five times less than Rtheta_j_c of the device alone.
the second trace on fig. 1 shows 120A 50% from 1-4 kHz at Tc = 80C, Tj =
150C. admittedly 2kHz is probably a lot faster than the heatsink thermal time constant, but the average is still 60A, without looking at switching loss.
the curves themselves have a Tc spec (80C & 110C) as well as Tj = 150C, hence the 70K dT figure I used to work out the thermal impedance required. The numbers just dont stack up. I'd believe that curve for intermittent pulsed operation, but not continuous.
if its 120A at 150C Tj then fig. 6 gives Vce = 6V, for Pon = 720W, IOW
360W average. shove that down 0.5K/W and voila, 180K dT (assuming perfect heatsink & thermal interface). then add in switching loss, which is pretty large.
IMO anyone who looks at fig. 1 and thinks "wow, I can do 120A at 2kHz" is in for an unpleasant surprise.
I prefer decent thermal models to Ztheta curves. kudos to infineon. some of their spice models have a thermal feedback term too, making full electro-thermal simulation straightforward in spice (assuming, as always, that your [thermal] models are meaningful).
it should be trivial nowadays for manufacturers to develop highly accurate thermal models - 3D FEA. After all, they know all the material properties and dimensions. Hell, teledeltos paper would do the trick. Or a fish tank and some perf sheet. Or a PhD and a month of algebra.
have you seen the 3-D SOA+lifetime curves in the siliconix mospower apps book? lovely.
I have seen Semikrons mathcad models, which are exactly what you describe - curve fits to measured data for device parameters, both electrical and thermal. then a transient analysis that models the thermal dynamics as well as the electrical ones.
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