I/O switching speed of Xilinx spartan 6 or Altera EP4CE10
Jan 15, 2017 21 Replies
T
Tim Wescott
If you shift the carrier by 180 degrees at audio, you shift the carrier
180 degrees at RF. If you reduce the signal by a factor of five at audio, you reduce the signal by a factor of five at RF.
That's just how SSB works. Direct-to-RF PSK just does all of it's manipulations to an RF carrier, and forgoes making an audio signal that's then converted up to RF.
Tim Wescott
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K
kristoff
Hi Tim,
That's correct. Just to have something that I can play with.
The big advantage of direct synthesis is that I do not need anything else except equipement that I already have.
Just a small wire from output of the DDS next to the antenna of my FT857D (as SSB receiver) and that should be enough to get the signal back into my PC using my standard "digimode" setup. If I have done everything correctly, fldigi (digimode application on linux- should then be able to decode what I have created on the FPGA.
After all, this started as a small exercise for verilog for something that is -more or less- usefull. If the PSK31 encoding part works, we can then work on the analog part: add filters to "clean up" the signal, amplify, antenna-adjusment, ... but I'll do that together with some people who are better on "analog" then myself. :-)
The question on "how fast can an I/O port on a FPGA actually switch" just came up while working on this.
Another element I like to explore is the question what an implemention on a CPLD looks like. I have two boards with cheap altera CPLDs. It's interesting to see what the lack of a hardware multiplying unit (as compaired to a FPGA) does to a design.
Cheerio! Kr. Bonne.
(or, as we hams like to say)
73 kristoff - ON1ARF
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