How to fix LTspice schematic

Robert Baer a =E9crit :

Actually playing with LTspice (V2.17i, May 2006) but not a specialist at all, I loaded your design and let it run. What error message? I don't get any. However, I don't think your circuit is doing what you want it to do... or maybe the simulation is too short.

Thanks, Jenalee K.

Robert Baer a écrit :

Actually playing with LTspice (V2.17i, May 2006) but not a specialist at all, I loaded your design and let it run. What error message? I don't get any. However, I don't think your circuit is doing what you want it to do... or maybe the simulation is too short.

Thanks, Jenalee K.

The first thing that I noticed is that the op-amps are being powered by a negative voltage, -12VDV

No, they are powered correctly. He inverted the sources and then specified them as negative outputs, so they come out right.

(Snip netlist)

Hi, Robert -

I do not get an error message, either. What does the message say?

When you get past the message, you will probably find that you need to specify Vhigh for A1. And, it would be a good idea to specify its Trise.

Cheers, John

"Robert Baer" wrote in message news:DRGSg.7187$ snipped-for-privacy@newsread2.news.pas.earthlink.net...

Here you go..... Heretic mode voltage regulation with heretic mode current limiting to protect your ball bag......

Jeorg would use a 40106 but this one doesn't work with a 4069....either.

Somehow I just know, for some reason, you felt the need to draw a shitty looking circuit diagram. So mine looks prettier too.

Bonus!!

DNA

Version 4 SHEET 1 1832 680 WIRE 64 -96 32 -96 WIRE 1328 -96 64 -96 WIRE 1664 -96 1408 -96 WIRE 704 0 -64 0 WIRE 928 0 848 0 WIRE 1040 0 992 0 WIRE 1072 0 1040 0 WIRE 1136 0 1072 0 WIRE 1248 0 1200 0 WIRE 1280 0 1248 0 WIRE 1344 0 1280 0 WIRE 1456 0 1408 0 WIRE 1488 0 1456 0 WIRE 1568 0 1488 0 WIRE 704 96 704 80 WIRE 1040 112 1040 0 WIRE 1248 112 1248 0 WIRE 1456 112 1456 0 WIRE 544 144 512 144 WIRE 64 176 64 -96 WIRE 176 176 64 176 WIRE 288 176 240 176 WIRE 400 176 352 176 WIRE 512 176 512 144 WIRE 512 176 464 176 WIRE 656 176 512 176 WIRE 64 192 64 176 WIRE 960 192 1040 112 WIRE 1168 192 1248 112 WIRE 1376 192 1456 112 WIRE 960 224 960 192 WIRE 1072 224 1072 0 WIRE 1168 224 1168 192 WIRE 1280 224 1280 0 WIRE 1376 224 1376 192 WIRE 1488 224 1488 0 WIRE 1568 224 1568 0 WIRE 64 320 64 272 WIRE 96 320 64 320 WIRE 960 320 960 288 WIRE 1168 320 1168 288 WIRE 1376 320 1376 288 WIRE 64 384 64 320 WIRE 144 384 64 384 WIRE 272 384 208 384 WIRE 704 384 704 192 WIRE 704 384 336 384 WIRE 896 384 960 320 WIRE 1104 384 1168 320 WIRE 1312 384 1376 320 WIRE -64 416 -64 0 WIRE 64 416 64 384 WIRE 704 416 704 384 WIRE -64 528 -64 496 WIRE 64 528 64 496 WIRE 64 528 -64 528 WIRE 208 528 208 400 WIRE 208 528 64 528 WIRE 336 528 336 400 WIRE 336 528 208 528 WIRE 704 528 704 496 WIRE 704 528 336 528 WIRE 848 528 848 80 WIRE 848 528 704 528 WIRE 896 528 896 384 WIRE 896 528 848 528 WIRE 928 528 896 528 WIRE 1072 528 1072 288 WIRE 1072 528 992 528 WIRE 1104 528 1104 384 WIRE 1104 528 1072 528 WIRE 1136 528 1104 528 WIRE 1280 528 1280 288 WIRE 1280 528 1200 528 WIRE 1312 528 1312 384 WIRE 1312 528 1280 528 WIRE 1344 528 1312 528 WIRE 1488 528 1488 288 WIRE 1488 528 1408 528 WIRE 1568 528 1568 304 WIRE 1568 528 1488 528 WIRE 1664 528 1664 -96 WIRE 1664 528 1568 528 WIRE 1696 528 1664 528 WIRE -64 560 -64 528 FLAG -64 560 0 FLAG 176 192 0 FLAG 1696 528 VOUT IOPIN 1696 528 Out FLAG 32 -96 VFB IOPIN 32 -96 Out FLAG 544 144 DRV IOPIN 544 144 Out FLAG 288 192 0 FLAG 400 192 0 FLAG 96 320 LIM IOPIN 96 320 Out SYMBOL nmos 656 96 R0 WINDOW 0 65 35 Left 0 WINDOW 3 63 61 Left 0 SYMATTR InstName M1 SYMATTR Value Si9420DY SYMBOL res 688 400 R0 WINDOW 0 38 48 Left 0 WINDOW 3 39 72 Left 0 SYMATTR InstName RSNS SYMATTR Value 100R SYMBOL ind2 688 -16 R0 WINDOW 0 39 55 Left 0 SYMATTR InstName L1 SYMATTR Value 1m SYMATTR Type ind SYMBOL ind2 864 96 R180 WINDOW 0 50 56 Left 0 WINDOW 3 43 32 Left 0 SYMATTR InstName L2 SYMATTR Value 9m SYMATTR Type ind SYMBOL cap 992 -16 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C1 SYMATTR Value 470p SYMBOL cap 992 512 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C2 SYMATTR Value 470p SYMBOL diode 1056 224 R0 WINDOW 0 -48 16 Left 0 WINDOW 3 -48 38 Left 0 SYMATTR InstName D2 SYMATTR Value DID SYMBOL diode 976 288 R180 WINDOW 0 46 48 Left 0 WINDOW 3 37 25 Left 0 SYMATTR InstName D1 SYMATTR Value DID SYMBOL cap 1200 -16 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C3 SYMATTR Value 470p SYMBOL cap 1200 512 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C4 SYMATTR Value 470p SYMBOL diode 1264 224 R0 WINDOW 0 -51 15 Left 0 WINDOW 3 -49 38 Left 0 SYMATTR InstName D4 SYMATTR Value DID SYMBOL diode 1184 288 R180 WINDOW 0 49 46 Left 0 WINDOW 3 38 24 Left 0 SYMATTR InstName D3 SYMATTR Value DID SYMBOL cap 1408 -16 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C5 SYMATTR Value 470p SYMBOL cap 1408 512 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C6 SYMATTR Value 470p SYMBOL diode 1472 224 R0 WINDOW 0 -44 11 Left 0 WINDOW 3 -44 35 Left 0 SYMATTR InstName D6 SYMATTR Value DID SYMBOL diode 1392 288 R180 WINDOW 0 47 51 Left 0 WINDOW 3 38 29 Left 0 SYMATTR InstName D5 SYMATTR Value DID SYMBOL res 1424 -112 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName RF SYMATTR Value 48E6 SYMBOL res 48 176 R0 WINDOW 0 43 44 Left 0 WINDOW 3 41 67 Left 0 SYMATTR InstName RG SYMATTR Value 100K SYMBOL res 1552 208 R0 WINDOW 0 45 34 Left 0 WINDOW 3 45 57 Left 0 SYMATTR InstName RL SYMATTR Value 1E6 SYMBOL voltage -64 400 R0 WINDOW 0 42 45 Left 0 WINDOW 3 45 70 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName VIN SYMATTR Value 50V SYMBOL res 48 400 R0 WINDOW 0 46 44 Left 0 WINDOW 3 44 68 Left 0 SYMATTR InstName RLIM SYMATTR Value 1K SYMBOL Digital\\\\inv 176 112 R0 SYMATTR InstName A1 SYMATTR SpiceLine Vhigh=5 Vlow=0 Trise=100n Tfall=100n Td=100n SYMBOL Digital\\\\inv 336 320 M0 SYMATTR InstName A2 SYMATTR SpiceLine Vhigh=5 Vlow=0 Trise=100n Tfall=100n Td=100n SYMBOL Digital\\\\inv 208 320 M0 SYMATTR InstName A3 SYMATTR SpiceLine Vhigh=5 Vlow=0 Trise=100n Tfall=100n Td=100n SYMBOL Digital\\\\inv 288 112 R0 SYMATTR InstName A4 SYMATTR SpiceLine Vhigh=5 Vlow=0 Trise=100n Tfall=100n Td=100n SYMBOL Digital\\\\inv 400 112 R0 SYMATTR InstName A5 SYMATTR SpiceLine Vhigh=5 Vlow=0 Trise=100n Tfall=100n Td=100n TEXT 720 -32 Left 0 !K1 L1 L2 1 TEXT 288 584 Left 0 !.tran 0 1 1u 1n uic TEXT 288 560 Left 0 !.MODEL DID D(RON=10m)

a

Yeah, right. So the voltage source "+" terminal is really negative. Seems like an odd way to do it. ... Johnny

That might help; how does one specify Vhigh and Trise for A1? I was also wondering abuut a power supply for the inverter, but since this is an emulator, maybe one does not need to be specified?

Thanks; will give this a try. LTspice is installed on a different HD and OS, so it will be a while before i can do that.

Yes, it does seem odd, except when one wishes to plot supply current and want it to read positive....

TPS2818

specified

Seems

Didn't mean to cast aspersions, Robert - I thought that there had to be a reason. ... Johnny

I am running ver 2.18s, Sept 2006. Error message is: Singular matrix: check node m1#gate Iteration No.2 OK

..and it is *not* "OK"!

No offence taken; i am just a little wierd...

Don't know about the inverter supply, but for Vhigh/low and Trise/fall, right-click the inverter, then copy the following into the "SpiceLine" attribute, (edit to suit).:-

Vhigh=12 Vlow=0 Trise=100n Tfall=100n Td=100n

(Thanks to DNA - I found this in his alternative to your circuit.)

When I first ran this simulation, I got the same error as you, but after adding the above line to the inverter attributes, I get a different error:-

Fatal Error: Singular matrix: check nodes n013 and u1:1:va+ Iteration No. 2

... Johnny

Add some resistance between A1 output and the gate and see if that helps.

You might also need some resistance between L2 and C1.

John

I got something like that also. No clues as what to fix or what changes are needed.

That circuit he gave is strange:

1) "Rl" is not from output to ground, where a practical load would go. 2) R1 allows Vout to go to 1.2KV with a small ripple; without Rl, the output only goes to 500V with a lot of ripple. 3) Increasing Rf by a factor of 5 has no effect on output voltage. 4) Output voltage ramps up in a *linear* fashion. 5) Have not found what limits/controls the output voltage. 6) M1 operates in the linear mode, but "switches between two current levels. 7) Looks like the output could be in the 10KV region with minor mods (*not* changing the multiplier).

error:-

This surprises me - when I manually calculate feedback with the given values, the feedback voltage to the inverters is 2.5V as it should be for

1kV output. The ripple is determined by the current limit via the 100R resistor.

Shouldn't it do this?

See my reply to >3)

levels.

I should point out that I'm a complete novice to LTSpice, with 2 days experience. Perhaps you should try posting this problem to the Yahoo LTSpice group.

... Johnny

Robert -

The inverter is not your problem. Don't worry with trying to simulate a TPS2818 yet.

It looks like you are trying to simulate a regulated high voltage power supply. Except for the effects of diode capacitance, the input to U2+ will remain low until D3 and D4 avalanche. Is that what you want? How much voltage across R1 do you desire?

It would be much better if you posted your requrements rather than a SPICE netlist.

Cheers, John

...and *where* does that "2.5V" value come from????? Oh, i forgot one other strange item: the lines / wires on the diodes are *not* at right angles! How the &#$()#$ was that done???