How to define a counter whose width is big enough to hold integer 27?

Hi, Sorry, everyone who participate in this discussion.

After finishing my code, I wrote log2() function and finally found that I didn't use it at all and actually use the following format before having read Rick suggestions.

signal Count : integer range 0 to N;

instead of

signal Count : unsigned(log2(N)-1 downto 0);

KJ: he says that "M := M mod 2;" is not equal to: "M := M/2;" I don't know why? Can you list a digital example to show your point?

Thank you.

Weng

Reply to
Weng Tianxiang
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No example required; they're completely different operators. mod is the remainder. / is the quotient.

That's like asking for an example to prove that / and + are different.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
 
Email address domain is currently out of order.  See above to fix.
Reply to
Rob Gaddi

And, of course, in VHDL, you can say : signal blat : integer range 0 to 27;

And VHDL figures out that you need 5 bits to represent that. You can use this in the port definitions between modules, too. Such as :

entity blah is port ( state : out integer range 0 to 27 );

One thing you have to keep in mind is what the logic might do if some value comes in from outside which exceeds the declared range but fits in the number of bits required to represent that. I'm assuming that synthesis tools don't protect against that.

Jon

Reply to
Jon Elson

What???!!! You are thinking of operations on... no, that's not right.... I don't know what you are thinking of.

You can define your function any way you want. You can redefine the mod operator to be the same as the divide operator. But if you do that I can't help you.

Try coding this up and see if it works.

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Rick
Reply to
rickman

No, but if you use the integer type simulation will catch it. Interesting point though. Something to be careful about in the system design. I seem to recall a rocket falling from the sky from a system design issue because of module reuse without catching an incompatible requirement.

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Rick
Reply to
rickman

There are three errors in your design, all of which have been pointed out:

  1. ceil(log2()) is needed, not log2().
  2. To include N, you need to use ceil(log2(N+1))-1 down to 0, not ceil(log2(N))-1 downto 0. Example: N=8 will require four bits to represent 8, not 3 bits
  3. M/2 is not equal to M mod 2 for integers. Example: int(5/2) = int(2.5) = 2; 5 mod 2 = 1. The mod operator gives you the remainder of the division, not the quotient

Kevin Jennings

Reply to
KJ

Why does everyone keep saying to use the ceiling function of log2(), then they add 1 to N before computing it? Isn't it simpler to just bloody take the floor of log2() and skip adding the 1?

Then Weng has a compulsion to calculate a result that he then has to subtract 1 from before using just because that is what he is used to seeing in array declarations.

Maybe I've had too much caffeine, but all this seems a bit absurd.

BTW, your first two points are based on using real functions, no? So it would need to be to_integer(ceil(log2(real(N+1))))? This really pushes it over the top for me.

Weng is not using real routines, but is writing his own log2() function for an integer input and integer output. But in reality it is ceil_log2_of_N+1() as it returns a value 1 too large to be log2.

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Rick
Reply to
rickman

Different yes, not simpler or harder. Either way there is an addition and a log function to perform.

No they are not.

What I use is the recursive version of the log2 function from the VHDL FAQ that I posted earlier and I have a separate ceil_log2 function that returns ceil(log2(N)). Both the ceil_log2 and the log2 functions have natural arg uments and return natural.

I use the log2 function from VHDL FAQ rather than ieee.math_real.log2 becau se I want something that is synthesizable and works with signals not just f or computing constants. y

Reply to
KJ

I don't follow what you are saying. Using a floor_log2() function means you skip adding the 1 to the input parameter and also skip subtracting the 1 to use it in the range specification. The point is the log2() function is not really the correct function for calculating the range. So why adjust it three ways when you can adjust it just once?

1st adjustment, use ceiling function. Second adjustment, add 1 to the input value. Third adjustment, subtract 1 from the result to get the range high value.

---or---

Just use the floored log2() function which is actually the same as the integer version of log2(). So maybe that's no adjustment at all?

I'd like to see your ceil_log2 function. Is it just log2() with a 1 subtracted from the input and a 1 added to result?

Yes, an integer log2 function has been discussed here, it just wasn't written 100% correctly.

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Rick
Reply to
rickman

Hi Rick and KJ,

Your are right. The only error "M := M mod 2;" should be "M := M / 2;"

KJ saying that it has 3 errors doesn't make sense.

Weng

Reply to
Weng Tianxiang

Actually if i used integer_bit_width(N) instead of log2(N), there are no confusions here, no ceiling or floor.

What I want is the bit width of an integer.

My only error "M := M mod 2;" should be "M := M / 2;"

for integer 8, return is 4; if 7, return is 3. Very simple.

Of cause I learn 2 things from this post:

  1. A constant uplimit can be generated by a function with constant input parameters.

  1. A void use operator mod that is more complex than what you think.

Thank you everyone.

Weng

The following first post by KJ causes Rick's doubt:

What exactly is the issue? ieee.MATH_REAL defines a log2 function that can be used to define the upper bound. Actually what you want is ceil(log2(N))

Kevin

I jusu ignored KJ' above info.

Reply to
Weng Tianxiang

Yes, you can invent an arbitrary function to return any value you want. So why not write it as vector_high_bit and save the subtraction? It then maps perfectly to the integer function log2(N) and you are done.

function vector_high_bit(integer: N) return integer is begin return log2(N); end vector_high_bit;

Even that name it too wordy for me, but it helps to be descriptive. I program software in Forth (very efficient and all about simplicity) and hardware in VHDL (very wordy tending toward the complex). Sometimes the contrast is very annoying.

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Rick
Reply to
rickman

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