Hi, I am trying to use the VGA display on the ML402 xilinx board, with V2SX35 FPGA on it. I am basically working with the reference desig provided by xilinx for ML402 board. I am using EDK7.1i and ISE7.1.03.
The problem I have is that I don't get any display on the VGA screen usin the reference design ("slideshow" and "bootload"). But, when I use th design provided by Xilinx in the CF card, I am able to get the display o the VGA screen!!
Also, when I run my software on the hardware system configured on the FPG by the default design, I can drive the VGA output!!
The only difference I see is that the default design uses system0.bit an system1.bit to configure the FPGA prior to downloading the catua configuration bit-file. I cannot find the source code for the system0.bi bit-file generation.
There seems to be some issue with DCM module in V4 using EDK7.1i. XIlin provided some nullBitStreams, but I cannot get my system work using th same.
Can someone help me with this issue. Any suggestion is appreciated.
Thanks, Krishna.
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