Hi all,
I have designed a DDC component with 2 outputs representing the I path and the Q path outputs. Simulation in Simulink works fine.
However when I did hardware cosim, the Q path hardware cosim output is fine but the I path hardware cosim output seem to have incur noise as that output seems to output a waveform that is off set by a magnitude of 2000 in the timescope domain. I would appreciate if some one has an answer to this.
I do suspect it could be possible due to a limit on the maximum hardware oversampling of my FIR Compiler to not be more than 5 as I saw before on the manual that Virtex can allow components to run at up to 500 MHZ which happen to be 5 times than the original oscillator provided on the development board. Do tell me if I was right.
Thank You.
Regards.